3D Memory Stack Layout for Independent Word and Bit Line Control
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Solution Overview
Problem
Three-dimensional memory devices face electrical challenges that hinder their performance and efficiency.
Innovation Solution
A memory device with a stack structure comprising a memory array stack and a staircase stack, insulated and conductive films, pillar elements, and memory cells connected through bit and word lines, allowing independent control of word line and bit line states using specific voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional memory devices are used, then high bit density is achieved, but electrical problems occur that hinder performance and efficiency
Solution Approach 1:
The memory device is divided into separate memory array stacks and staircase stacks, with distinct word line and bit line structures. This segmentation allows independent control and optimization of electrical characteristics for each component, resolving the electrical performance issues while maintaining high bit density through the three-dimensional stacked architecture.
Solution Approach 2:
The patent introduces separate word line switches and bit line switches as intermediary components between the control circuits and the memory cells. These intermediary switches provide independent electrical control paths, allowing precise management of voltage and current flow to selected memory cells without affecting other cells, thereby improving electrical reliability.
2Ease of operation
If word line voltage and bit line voltage are applied simultaneously to select a memory cell, then the selected memory cell can be turned on, but all bit lines may be inadvertently turned on or off causing interference
Solution Approach 1:
The control circuitry is segmented into separate word line control and bit line control paths, with independent switches for each. This allows the word line switch to be activated first to prepare the word line, followed by bit line switch activation to enable the selected bit line, ensuring that only the intended memory cell is accessed without interfering with other bit lines.
Solution Approach 2:
The word line switch is activated in advance before the bit line voltage is applied. This preliminary action ensures that the word line is properly prepared and isolated before the bit line connection is established, preventing inadvertent turning on or off of multiple bit lines and eliminating interference with unselected memory cells.
Data Source
AI summary
A memory device and a method for operating a memory device are provided. The memory device includes a stack structure including a memory array stack and a staircase stack, an insulating film on the memory array stack, a conductive film on the staircase stack and on a sidewall of the insulating film, a pillar element on the staircase stack and passing through the conductive film, and memory cells in the memory array stack and electrically connected to the pillar element.