3D Memory Cell Conductive Line Layout for Leakage and Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and reducing parasitic capacitance while managing leakage current and threshold voltage effectively in three-dimensional memory cells.
Innovation Solution
The semiconductor device incorporates a horizontal conductive line with a triple work function electrode structure, comprising a high work function electrode at the center and low work function electrodes at both ends, along with a vertical conductive line and a data storage element, to reduce electric fields and leakage current, thereby enhancing integration and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer conductive line is used, then the device structure is simple, but the leakage current increases and threshold voltage control deteriorates
Solution Approach 1:
The conductive line is divided into multiple segments with different work functions (first, second, and third work function electrodes) arranged in sequence. Each segment serves a specific function: the first and third electrodes with lower work functions reduce electric fields near the vertical conductive line and data storage element to minimize leakage, while the second electrode with higher work function provides stable threshold voltage control. This segmentation resolves the contradiction by improving reliability through targeted electric field management while maintaining reasonable structural complexity.
Solution Approach 2:
Different regions of the conductive line are assigned different work function characteristics tailored to local requirements. The regions adjacent to the vertical conductive line and data storage element use lower work function materials to reduce parasitic capacitance and leakage current, while the central region uses higher work function material for stable threshold control. This local quality differentiation directly addresses the leakage current issue without uniformly increasing device complexity.
2Quantity of substance
If memory cell density is increased through 3D stacking, then memory capacity improves, but parasitic capacitance increases
Solution Approach 1:
The conductive line is segmented into multiple work function regions that collectively reduce the total parasitic capacitance. By distributing the electric field management across multiple segments with optimized work functions, the structure achieves lower overall parasitic capacitance compared to a single-layer design, enabling higher memory cell density in 3D stacked configurations.
Solution Approach 2:
The conductive line employs a composite structure combining materials with different work functions (e.g., tungsten or titanium nitride for high work function, and doped polysilicon for lower work function). This composite approach allows simultaneous optimization of different regions to minimize parasitic capacitance while maintaining electrical performance, thus supporting increased memory cell density.
3Reliability
If a triple work function electrode structure is used, then leakage current reduces and threshold voltage control improves, but manufacturing complexity increases
Solution Approach 1:
The conductive line fabrication is divided into sequential deposition steps for different work function materials, with each step using standard semiconductor manufacturing techniques. The segmented structure allows independent optimization of each layer's properties while following a systematic fabrication flow, making the complex structure manageable through established process modules.
Solution Approach 2:
The manufacturing process controls the work function parameter by selecting appropriate materials and doping conditions for each electrode segment. By precisely controlling material composition and doping levels during fabrication, the process achieves the desired threshold voltage characteristics while using conventional manufacturing parameters and techniques.
4Reliability
If electric field intensity is reduced, then leakage current decreases, but memory cell integration density may be compromised
Solution Approach 1:
The conductive line is segmented to reduce electric fields only in critical regions adjacent to the vertical conductive line and data storage element, while maintaining appropriate field strength in the channel region. This localized electric field management reduces leakage current without compromising the overall integration density of memory cells.
Solution Approach 2:
Different work function characteristics are applied locally to different regions of the conductive line. Regions where electric field reduction is needed (near vertical conductive line and data storage element) use lower work function materials, while the channel region maintains higher work function for proper device operation. This local differentiation achieves leakage reduction while preserving integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The triple work function electrode structure improves leakage current characteristics and reduces parasitic capacitance, allowing for higher integration and lower power consumption in three-dimensional memory cells.
Implementation Method 1
a horizontal conductive line with a triple work function electrode structure, including a high work function electrode at the center and low work function electrodes on both sides, which reduces electric fields and enhances threshold voltage
Implementation Method 2
forming a vertical opening by etching the stack body; forming horizontal recesses by recessing the first and second sacrificial layers from the vertical opening
Implementation Method 3
The first and second low work function electrodes each include N-type dopant doped polysilicon
Data Source
AI summary
A semiconductor device may include: a lower structure; a horizontal layer spaced apart from the lower structure and extending along a direction parallel to the lower structure; a vertical conductive line extending along a direction perpendicular to the lower structure and coupled to a first side end of the horizontal layer; a data storage element coupled to a second side end of the horizontal layer; and a horizontal conductive line extending along a direction crossing the horizontal layer and including a sloped side facing the vertical conductive line.