3D Memory Access-Line Sharing for Higher Integration Density
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Solution Overview
Problem
Conventional 3-dimensional memory devices face limitations in integration due to the large areas of sub-wordline driver arrays and sense amplifier arrays, which exceed the area of memory cells, leading to decreased integration and increased costs when using different manufacturing processes.
Innovation Solution
The proposed 3-dimensional memory device shares bitlines and wordlines through circuit elements, allowing for reduced areas of sub-wordline driver and sense amplifier arrays by connecting them to global lines, thereby improving integration without time delays in read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sub-wordline driver arrays and sense amplifier arrays are designed with sufficient area to handle all bitlines and wordlines, then reliable data read operations are achieved, but the total device area increases and integration density decreases
Solution Approach 1:
The patent divides the bitline and wordline connections into multiple segments, each handled by a separate circuit element. Multiple circuit elements share the total set of access lines, so each element only needs to handle a portion of the bitlines and wordlines. This segmentation reduces the area required for each individual circuit element while maintaining overall system reliability through distributed architecture.
Solution Approach 2:
Each circuit element is designed to handle multiple functions: it connects to both bitlines and wordlines, and can operate with different combinations of these lines. The circuit elements are universally applicable across different memory cell slots, reducing the need for dedicated large-area arrays and enabling area-efficient design through functional sharing.
2Manufacturing precision
If separate manufacturing processes are used for logic arrays and memory cells to optimize各自 performance, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent designs the sub-wordline driver arrays and sense amplifier arrays with universal circuit elements that can be manufactured using the same process as memory cells. This universal design approach allows a single optimized manufacturing process to produce both logic and memory components, reducing device complexity and cost while maintaining manufacturing precision through process consistency.
Data Source
AI summary
A 3-dimensional memory device, including: memory cell slots deployed in a first horizontal direction, wherein each of the memory cell slot includes: memory cells deployed in a second horizontal direction and in a vertical direction; first access lines arranged in the vertical direction and deployed in the second horizontal direction, wherein the first access lines are one type of lines among (i) wordlines connected to each of gate terminals of each of the memory cells and (ii) bitlines connected to each of drain terminals of each of the memory cells; and second access lines arranged in the second horizontal direction and deployed in the vertical direction, wherein the second access lines are a different type of lines among (i) wordlines connected to each of the gate terminals of each of the memory cells and (ii) bitlines connected to each of the drain terminals of each of the memory cells.