3D Memory Redundant Line Sharing for Space-Efficient Repair
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Solution Overview
Problem
Existing repair methods for 3D memory devices face limitations due to the space required for redundant bit lines and word lines, which become thinner and more prone to breakdowns, leading to defects like opens or shorts between bit lines or word lines.
Innovation Solution
The memory device employs redundant bit lines and word lines that share a page buffer or decoder unit, respectively, reducing the space needed for repairs by connecting them through common lines to different page or decoder units, allowing efficient replacement of defective lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant bit lines are provided for each page buffer, then repair capability is improved, but space consumption increases
Solution Approach 1:
The patent merges redundant bit lines from different page buffers into a shared pool. Specifically, redundant bit lines BL_R1 and BL_R2 from different page buffers are connected to a common second page buffer through a common line, allowing a single redundant bit line to serve multiple page buffers and reducing total space requirements
Solution Approach 2:
The patent makes redundant bit lines universal by enabling a single redundant bit line to replace defective bit lines in multiple different page buffers. The common line CL allows the redundant bit line to be dynamically assigned to different page buffers based on which one contains the defective bit line, achieving multi-functional usage
2Reliability
If redundant word lines are provided for each decoder unit, then repair capability is improved, but space consumption increases
Solution Approach 1:
The patent merges redundant word lines from different decoder units into a shared pool. Redundant word lines WL_R1 and WL_R2 associated with different decoder units are connected to a common second decoder unit through a common line, allowing shared usage and reducing total space
Solution Approach 2:
The patent makes redundant word lines universal by enabling a single redundant word line to replace defective word lines in multiple different decoder units. The common line allows dynamic assignment of the redundant word line to different decoder units based on defect location, achieving multi-functional replacement capability
3Quantity of substance
If the number of layers is increased in 3D memory, then storage capacity is improved, but gate layer thickness decreases leading to more defects
Solution Approach 1:
The patent prepares redundant bit lines and word lines in advance as backup resources before defects occur. When defects are detected in the main bit lines or word lines due to thinning from increased layering, the system can immediately switch to the pre-prepared redundant lines, cushioning against the reliability degradation caused by higher layer counts
Data Source
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AI summary
A memory device is provided. The memory device includes: a first cell region provided in a first layer and including a first bit line and a first redundant bit line; a second cell region provided in a second layer and including a second bit line and a second redundant bit line; a peripheral region provided in a third layer and including first page buffers configured to be respectively connected to the first bit line and the second bit line, and a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line; and a control circuit configured to: based on the first bit line being defective, replace the first bit line with the first redundant bit line; and based on the second bit line being defective, replace the second bit line with the second redundant bit line.