3D Memory Staircase Pads with Connected Vertical Structures
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost and practical constraints of advanced processing equipment needed for finer pattern formation, leading to a need for three-dimensional semiconductor memory devices with improved reliability and increased integration.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate featuring a cell array and connection region, vertically stacked electrodes in a staircase structure, and vertical structures that penetrate both regions, including first and second vertical structures with specific spacings and connections to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and high cost of advanced processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked vertically above the substrate, with electrodes extending through intermediate layers to form vertical channels. This dimensional transition enables significantly higher integration density without requiring proportionally more advanced planar processing equipment, as the vertical stacking utilizes the third dimension to pack more memory cells within the same footprint area.
2Quantity of substance
If vertical structures are made closer together to increase integration, then integration density improves, but structural stability deteriorates leading to potential collapse
Solution Approach 1:
The vertical structures are segmented into discrete memory cell layers separated by intermediate layers. Each layer is independently formed with its own electrode structures and memory elements, allowing the vertical channel to be divided into multiple functional segments. This segmentation provides structural support at each layer interface, preventing continuous vertical structures from collapsing while maintaining high integration density through close spacing of the segmented layers.
Solution Approach 2:
Different regions of the vertical structure have different properties: the memory cell layers contain active memory elements with specific electrical characteristics, while the intermediate layers provide structural support and electrical isolation. The electrode structures have varying cross-sectional areas and compositions at different heights to optimize both structural stability and electrical performance. This local differentiation allows the structure to maintain stability while achieving high integration through close spacing.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.