3D Memory Local Contact Structure for Wafer Stress Reduction
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Solution Overview
Problem
The challenge in 3D memory device fabrication lies in managing wafer bow and overlay control complexities, particularly due to the 'dishing' profile at the upper end of the slit structure, which complicates the deposition of materials and increases fabrication costs, especially as the level of 3D memory devices increases.
Innovation Solution
The proposed solution involves modifying the fabrication process by etching contact holes before the gate replacement and slit structure formation, allowing for the same conductive materials to be used for channel local contacts and slit structures, and merging their deposition processes to simplify overlay control and reduce local stress, thereby improving planarization and reducing the 'dishing' profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate materials and processes are used for channel local contacts and slit structures, then material optimization is achieved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent merges the channel local contact and slit structure into a single integrated structure formed by one continuous conductive material. This eliminates the need for separate materials and deposition processes, reducing fabrication complexity while maintaining the functional advantages of material optimization. The unified structure is formed in a single etch and fill operation, simplifying the overall manufacturing process.
2Manufacturing precision
If deposition processes are performed separately for channel local contacts and slit structures, then precise control is achieved, but overlay control complexity and fabrication cost increase
Solution Approach 1:
The patent combines the deposition of channel local contacts and slit structures into a single simultaneous deposition process. This eliminates overlay control issues between separate deposition steps while maintaining precise control over the combined structure. The single deposition event ensures automatic alignment and reduces fabrication complexity.
Solution Approach 2:
The patent performs preliminary patterning and preparation steps before the combined deposition, ensuring that the single deposition process can proceed with precise control. The preliminary actions include forming the conductive layer pattern and preparing the substrate, which enable the subsequent unified deposition to achieve both precision and simplicity.
3Reliability
If complex multi-material structures are used for channel local contacts and slit structures, then functional performance is improved, but wafer local stress increases
Solution Approach 1:
The patent uses a homogeneous single conductive material for both the channel local contact and slit structure portions. This material uniformity eliminates stress mismatches that would arise from interfaces between different materials, thereby reducing wafer local stress while maintaining the functional performance needed for both structures.
Data Source
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AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The slit structure includes a contact including a first contact portion and a second contact portion above the first contact portion and having a different material of the first contact portion. An upper end of the second contact portion of the slit structure is flush with an upper end of the channel local contact.