3D Memory Array Local Column Decoders
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high-speed operation and increased storage density while minimizing space for peripheral circuitry, particularly in three-dimensional memory arrays where programming speed is hindered by the need to change column addresses and global column decoders are not efficiently utilized.
Innovation Solution
A monolithic three-dimensional memory array design that includes selective connection of bit lines to sense amplifiers using selection circuits with level shifters, allowing programming without changing column addresses, which increases programming speed and reduces the need for global column decoders, thereby saving space and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If column addresses are changed during programming in existing memory designs, then programming can be performed across multiple columns, but programming speed is delayed because the column address cannot be changed until bit lines are discharged
Solution Approach 1:
The patent divides the memory array into multiple blocks, each with its own local column decoder. This segmentation allows different blocks to be programmed simultaneously with different column addresses, eliminating the need to wait for bit line discharge before changing column addresses. The local column decoders can be updated independently and in parallel, resolving the timing conflict between column address changes and bit line discharge requirements.
Solution Approach 2:
The patent introduces a block dimension to the traditional row-column memory addressing scheme. By adding the block level of organization above rows and columns, the system can perform programming operations in three dimensions (block, row, column) simultaneously. This dimensional expansion allows multiple column address changes to occur in parallel across different blocks, transforming a sequential operation into a parallel one and eliminating the programming delay.
2Adaptability or versatility
If global column decoders are used for multiple blocks, then column selection can be performed across the entire memory array, but space on the semiconductor die is increased
Solution Approach 1:
The patent segments the column decoding function by providing each block with its own local column decoder instead of using a single global column decoder for the entire memory array. This segmentation reduces the area required for column decoding circuitry because the local decoders can be smaller and more efficiently integrated within each block, while still providing full column selection capability across the entire array through coordinated block selection.
Solution Approach 2:
The patent adds the block dimension to the addressing hierarchy, allowing column selection to be performed in two stages: first selecting the block (which contains a local column decoder), then selecting the column within that block. This dimensional approach distributes the decoding functionality across multiple blocks rather than concentrating it in a single global decoder, reducing the overall space requirement while maintaining full adaptability for column selection across the entire memory array.
3Quantity of substance
If three-dimensional memory arrays are used to increase storage density, then more data can be stored in a given space, but programming speed is hindered by the need to change column addresses and the complexity of peripheral circuitry
Solution Approach 1:
The patent segments the three-dimensional memory array into multiple blocks, each capable of independent programming operations with local column decoders. This segmentation allows parallel programming across multiple blocks, significantly improving programming speed while maintaining high storage density. The local decoders reduce the complexity of peripheral circuitry by distributing the decoding function, eliminating the need for complex global column decoder switching mechanisms that would slow down programming in three-dimensional arrays.
Solution Approach 2:
The patent utilizes a three-dimensional memory structure with an additional block dimension stacked above the traditional row-column plane. This third dimension enables multiple row-column planes to be accessed and programmed simultaneously through different block selections, dramatically increasing programming throughput while maintaining high density. The block dimension provides a new degree of freedom for parallel operation, allowing the memory system to exploit spatial multiplexing across stacked layers without increasing peripheral circuitry complexity.
Data Source
AI summary
A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.