3D Memory Cell Array Structure With Local Charge-Storage Thickness
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Solution Overview
Problem
Existing two-dimensional semiconductor devices face limitations in integration due to the expensive equipment required for fine pattern formation, which restricts the increase in storage capacity per unit area.
Innovation Solution
A three-dimensional semiconductor memory device is developed, comprising a substrate with a peripheral circuit structure and a cell array structure that includes a stack of gate electrodes, a first source conductive pattern, and vertical channel structures in vertical channel holes. The vertical channel structures feature a data storage pattern on their sidewalls, a vertical semiconductor pattern, and a second source conductive pattern, with the thickness of the data storage pattern between the first and second source conductive patterns being greater than between the stack structure and the vertical semiconductor pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are highly integrated to increase storage capacity, then storage capacity per unit area is improved, but the manufacturing cost increases due to expensive processing equipment needed for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory cells are stacked vertically along the third dimension, enabling increased storage capacity per unit area without requiring finer lateral patterning, thus avoiding the need for expensive fine pattern formation equipment
2Quantity of substance
If the thickness of the data storage pattern between the stack structure and vertical semiconductor pattern is increased to improve data storage capacity, then storage capacity is improved, but the electrical characteristics and reliability may deteriorate due to increased resistance and potential manufacturing defects
Solution Approach 1:
The patent applies different thicknesses of the data storage pattern at different locations. The thickness between the stack structure and vertical semiconductor pattern is controlled to be less than the thickness between source conductive patterns, optimizing electrical characteristics in critical regions while maintaining adequate storage capacity in other regions
Data Source
AI summary
Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.