3D Memory and Control Logic Bonding for Denser DRAM Layouts
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature size and performance enhancements like faster speed and lower power consumption.
Innovation Solution
The method involves forming microelectronic devices with array regions, digit line exit regions, word line exit regions, and socket regions, using conductive and insulative materials, and specific structures like contact structures and routing tiers to optimize the arrangement and operation of control logic devices, allowing for more compact and efficient memory device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are formed using conventional processing conditions, then the memory array can be fabricated, but the control logic device configurations and performance are limited
Solution Approach 1:
The patent divides the control logic structure into multiple tiers (first tier, second tier, third tier) with different functions. The first tier includes control logic devices formed at lower temperatures, the second tier includes additional control logic devices, and the third tier includes routing structures. This segmentation allows each tier to be optimized for specific functions and formed under appropriate processing conditions, resolving the contradiction between performance and configuration flexibility.
Solution Approach 2:
The patent transitions from a conventional planar control logic structure to a three-dimensional multi-tier architecture. Control logic devices are distributed across vertical tiers rather than being confined to a single layer, enabling more complex configurations and improved performance while accommodating various processing conditions at different vertical positions.
2Productivity
If the memory device size is reduced to increase integration density, then more features can be integrated, but processing conditions and control logic configurations limit further size reduction
Solution Approach 1:
The patent utilizes vertical stacking with multiple tiers of control logic devices and routing structures to increase integration density without proportionally increasing the horizontal footprint. By distributing functionality across vertical tiers, the device achieves higher productivity while maintaining a compact form factor, overcoming the limitations of conventional planar scaling.
Solution Approach 2:
The patent implements a nested hierarchical structure where control logic devices, routing structures, and interconnects are organized in concentric tiers. The first tier control logic devices are nested within the overall device structure, the second tier control logic devices are nested above them, and routing structures are nested in the third tier, maximizing space utilization and integration density.
3Speed
If conventional control logic structures are used, then the memory array can function, but performance improvements like faster speed and lower power consumption are impeded
Solution Approach 1:
The patent segments the control logic functionality across multiple tiers, with the first tier handling primary control operations, the second tier providing additional control logic, and the third tier managing routing. This segmentation enables faster signal propagation and reduced latency compared to conventional single-layer structures, improving speed while distributing complexity across manageable tiers.
Solution Approach 2:
The patent forms control logic devices in the first tier before forming the memory array structures above them. This preliminary action allows the control logic to be pre-configured and optimized for high-speed operation, with subsequent processing steps building upon this foundation without compromising the performance-critical control logic structures.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.