3D Memory-Logic Processor for Non-Arithmetic Computing
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Solution Overview
Problem
Conventional processors based on two-dimensional integration face inefficiencies due to limited memory capacity, high data transfer latency, and inability to perform non-arithmetic functions, leading to slow performance in mathematical computing, computer simulation, pattern processing, and neural networks.
Innovation Solution
A discrete three-dimensional processor is designed with separate dice for three-dimensional memory arrays and logic circuits, allowing for optimized manufacturing and performance, enabling efficient computation of non-arithmetic functions and models through memory-based computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional integration is used for processor design, then manufacturing processes are simpler and costs are lower, but memory capacity is limited and data transfer latency is high
Solution Approach 1:
The patent transitions from conventional two-dimensional planar integration to three-dimensional vertical stacking architecture. Multiple logic circuit layers and memory layers are stacked vertically to increase memory capacity and improve data access efficiency without proportionally increasing the chip footprint, thereby resolving the contradiction between memory capacity and device complexity.
Solution Approach 2:
The patent implements a nested structure where logic circuits are embedded within or adjacent to memory layers in a vertical stack. This nesting approach allows memory and logic units to be closely integrated, enabling high-capacity memory while maintaining compact device structure and reducing data transfer distances.
2Speed
If processor and external memory are physically separated in von Neumann architecture, then device structure is simpler, but data transfer bandwidth is limited and latency is high
Solution Approach 1:
The patent merges memory and logic circuits into a unified three-dimensional processor structure where memory layers and logic layers are vertically integrated. This combination eliminates the physical separation between processor and memory, enabling high-speed data access and computation without the bandwidth limitations of external memory interfaces.
Solution Approach 2:
By transitioning to three-dimensional vertical stacking, the patent creates multiple layers of memory and logic circuits that can communicate through short vertical interconnects. This dimensional change dramatically reduces data transfer latency compared to horizontal communication in planar architectures, achieving high-speed processing with improved architectural efficiency.
3Adaptability or versatility
If logic-based computation is used for mathematical functions, then arithmetic operations are efficient, but non-arithmetic functions cannot be implemented
Solution Approach 1:
The patent implements a universal computing architecture where three-dimensional memory structures serve multiple functions: storing data, performing look-up table operations for non-arithmetic functions, and enabling both logic-based and memory-based computation. This multi-functionality allows the same hardware structure to handle arithmetic operations, transcendental functions, and special functions without requiring separate dedicated circuits.
Solution Approach 2:
The patent replaces traditional logic-circuit-based computation for non-arithmetic functions with memory-based computation using three-dimensional memory structures. Instead of using complex logic circuits to compute transcendental functions, the system uses pre-computed values stored in 3D memory, substituting mechanical logic operations with memory access and interpolation operations.
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises at least a portion of a logic/processing circuit and an off-die peripheral-circuit component of the 3D-M array(s). The preferred 3-D processor can be used to compute non-arithmetic function/model. In other applications, the preferred 3-D processor may also be a 3-D configurable computing array, a 3-D pattern processor, or a 3-D neuro-processor.