3D Memory-Logic Integration for Compact DRAM Contact Routing
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature size and performance enhancements like faster speed and lower power consumption.
Innovation Solution
The method involves forming microelectronic devices with array regions, digit line exit regions, word line exit regions, and socket regions, using conductive and insulative materials, and forming contact structures to facilitate electrical connections between digit lines, word lines, and control logic devices, allowing for vertical offsetting of control logic devices within the array regions to improve integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are formed using conventional processing conditions, then the memory array can be fabricated, but the control logic device configurations and performance are limited
Solution Approach 1:
The patent applies dimensionality change by vertically offsetting control logic devices relative to the memory array in the third dimension (Z-axis). Instead of expanding control logic devices horizontally within the same plane, the invention stacks them at different vertical levels, allowing multiple control logic devices to coexist without increasing the horizontal footprint. This vertical stacking enables more complex control logic configurations and improved performance while maintaining compatibility with conventional processing conditions.
2Area of stationary object
If the horizontal footprint of control logic devices is reduced, then memory device size decreases, but contact structure alignment complexity increases
Solution Approach 1:
The patent resolves the alignment complexity issue by transitioning from two-dimensional planar alignment to three-dimensional vertical alignment. Control logic devices are positioned at different vertical offsets relative to the memory array, with contact structures extending through intermediate layers to establish electrical connections. This vertical stacking approach reduces the horizontal footprint while managing alignment complexity through standardized via and contact formation processes.
Solution Approach 2:
The patent introduces intermediate structural elements (such as dielectric layers, conductive vias, and contact structures) that act as mediators between the vertically offset control logic devices and the memory array. These intermediary structures facilitate electrical connections while absorbing some of the alignment complexity, allowing the control logic devices to be vertically offset without directly increasing overall device complexity.
3Area of moving object
If feature dimensions are reduced to increase integration density, then device compactness improves, but processing conditions become more constrained
Solution Approach 1:
The patent circumvents processing constraints by utilizing the vertical dimension for device differentiation rather than relying solely on horizontal feature scaling. Control logic devices and memory cells are formed using similar processing conditions but are positioned at different vertical levels and have different horizontal footprints. This approach allows increased integration density through vertical stacking while maintaining processing condition flexibility, as the same fabrication processes can form structures at multiple vertical levels without requiring extreme miniaturization.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.