3D Memory Control Logic Stacking for Shorter Signal Routing
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Solution Overview
Problem
Conventional microelectronic devices face challenges in increasing integration density and performance due to processing conditions limiting control logic devices within memory devices, which impede size reduction and performance improvements.
Innovation Solution
A microelectronic device configuration with a control logic region overlying a memory array region, featuring a vertical arrangement of regions such as memory array, interconnect, and pad regions, allowing for enhanced signal transmission and improved signal integrity through direct vertical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control logic devices are placed within a base control logic structure underlying the memory array, then control operations can be performed on memory cells, but processing conditions limit the configurations and performance of control logic devices and impede size reduction
Solution Approach 1:
The patent transitions control logic devices from a planar arrangement beneath the memory array to a vertical arrangement above the memory array. This dimensional change allows control logic devices to be positioned in the vertical dimension rather than competing for horizontal space, enabling both compact footprint and improved processing conditions for high-performance control logic operations.
2Ease of manufacture
If control logic devices are arranged in a conventional planar manner, then the device can be manufactured with standard processes, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent employs vertical stacking to position control logic devices above the memory array in the vertical dimension. This approach maintains compatibility with standard semiconductor manufacturing processes while dramatically reducing the horizontal footprint by utilizing the vertical space above the memory array rather than expanding the device area horizontally.
3Area of moving object
If control logic devices are positioned close to memory cells for compact design, then integration density increases, but signal transmission distance and integrity become problematic
Solution Approach 1:
The patent positions control logic devices vertically above memory cells through direct vertical connections via contact structures. This vertical positioning achieves compact integration density while the direct vertical connection path minimizes signal transmission distance and maintains signal integrity, avoiding the routing complexities of planar arrangements.
4Reliability
If routing structures are used to connect control logic devices to memory cells, then electrical communication is established, but routing distances increase and signal transmission speed decreases
Solution Approach 1:
The patent extracts the connection path from complex horizontal routing structures and replaces it with direct vertical contact structures. By removing unnecessary routing layers and using direct vertical contacts between control logic devices and memory cells, signal transmission distance is minimized and speed is maximized while maintaining reliable electrical communication.
Data Source
AI summary
A microelectronic device includes a memory array region, a control logic region overlying the memory array region, and a pad region overlying the control logic region. The memory array region includes a stack structure including vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically underlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically overlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region includes control logic devices configured to effectuate control operations for the vertically extending strings of memory cells. The pad region includes conductive pad structures coupled to the control logic devices. Memory devices and electronic systems are also described.