3D Memory Peripheral Circuits for Low-Leakage High-Speed NAND
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory peripheral circuits face challenges in achieving high speed, low leakage current, high voltage, and small size simultaneously without increasing cost, particularly in 3D NAND Flash memory devices.
Innovation Solution
The use of 3D transistors in memory peripheral circuits, such as I/O circuits, page buffers, and word line drivers, replaces conventional planar transistors, allowing for a hybrid configuration that combines 3D and planar transistors in the same process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors are used in memory peripheral circuits, then manufacturing cost is reduced and fabrication process is simplified, but leakage current increases and circuit size cannot be reduced further
Solution Approach 1:
The patent transitions from planar (2D) transistors to three-dimensional (3D) transistors, specifically using FinFET architecture where the gate wraps around the channel in a three-dimensional configuration. This dimensional change provides superior gate control over the channel, reducing leakage current while maintaining compatibility with existing fabrication processes through modified etching and deposition steps.
Solution Approach 2:
The patent modifies key transistor parameters including increasing the gate-to-channel control ratio through 3D geometry, adjusting fin height and width dimensions, and optimizing gate electrode material composition. These parameter changes enable reduced leakage current and improved switching characteristics while maintaining manufacturability.
2Area of moving object
If planar transistors are scaled to smaller sizes, then memory density increases, but manufacturing complexity increases and cost increases
Solution Approach 1:
Instead of continuing to scale planar transistors to smaller dimensions which increases fabrication complexity, the patent adopts 3D FinFET architecture. This allows maintaining larger, easier-to-manufacture lateral dimensions while achieving smaller effective channel areas through vertical fin structures, thus reducing transistor footprint without proportionally increasing fabrication complexity.
Solution Approach 2:
The patent introduces dynamic control mechanisms in the 3D transistor design, including adjustable gate voltages that can dynamically optimize the on-state current and off-state leakage characteristics. This dynamic operation allows the same transistor structure to adapt to different operating conditions, reducing the need for multiple specialized transistor designs.
3Speed
If 3D transistors are used in memory peripheral circuits, then speed increases and leakage current decreases, but device complexity increases
Solution Approach 1:
The patent implements 3D FinFET transistors with gates that wrap around the channel sidewalls, providing enhanced electrostatic control and higher drive current capability. This three-dimensional gate structure increases switching speed and reduces leakage while the fin geometry can be optimized through standard semiconductor fabrication processes, balancing performance gains with manufacturing complexity.
Solution Approach 2:
The patent employs composite material structures in the 3D transistor design, including high-k dielectric materials for the gate insulator and metal gate electrodes, combined with silicon or silicon-germanium fin structures. These composite materials enable superior electrical performance and faster switching speeds while maintaining compatibility with existing CMOS fabrication processes.
Data Source
AI summary
In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.