3D Memory Peripheral Transistor Structure With Low-Resistance Contacts
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Solution Overview
Problem
Scaling down planar semiconductor devices to smaller sizes is challenging and costly, and 3D memory devices face issues with increased peripheral circuit areas and complexity, leading to higher leakage currents and manufacturing costs.
Innovation Solution
A 3D memory device architecture with a peripheral device and memory stack, featuring a transistor structure without a metal silicide blocking layer, where a metal silicide layer is used between source/drain regions and contact structures, simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If planar semiconductor devices are scaled down to smaller sizes, then device density is improved, but manufacturing cost and process difficulty increase
Solution Approach 1:
The patent transitions from planar 2D device architecture to 3D vertical stacking architecture. Multiple semiconductor layers are stacked vertically with through-silicon vias (TSVs) enabling inter-layer interconnection, thereby increasing device density without further reducing lateral dimensions and avoiding the manufacturing challenges associated with extreme planar scaling
2Productivity
If 3D memory device architecture is adopted, then density limitation is addressed, but peripheral circuit area and complexity increase
Solution Approach 1:
Peripheral circuits are moved from the planar substrate to vertical stacking architecture. Different functional layers (memory layers, peripheral circuit layers, I/O layers) are stacked vertically, with each layer containing specific circuit functions. This distributes complexity across multiple layers rather than concentrating it in a large planar area, reducing the footprint and improving heat dissipation
3Productivity
If 3D memory device architecture is adopted, then device density is improved, but leakage current increases
Solution Approach 1:
Different regions of the stacked device are assigned different functional qualities optimized for their specific purposes. Memory regions use high-density storage structures while peripheral circuit regions use low-leakage transistor designs. Through-silicon via regions are isolated with insulation layers to prevent leakage paths. This localized optimization reduces overall leakage current while maintaining high density
4Ease of manufacture
If metal silicide blocking layer is removed from transistor structure, then manufacturing process is simplified, but contact resistance may increase
Solution Approach 1:
The metal silicide blocking layer is completely removed from the transistor structure. Instead of using a blocking layer to prevent silicide formation in certain regions, the patent employs selective epitaxial growth to grow semiconductor material only in desired regions, and uses spacer structures to define active areas, thereby eliminating the blocking layer and simplifying the manufacturing process
Solution Approach 2:
Spacer structures serve as intermediaries to define the boundaries of active regions and control the formation of source/drain structures. The spacers physically separate regions where silicide should and should not form, replacing the function previously performed by metal silicide blocking layers while enabling better process control and reduced contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure reduces contact resistance and simplifies the fabrication process, lowering manufacturing costs and improving performance by optimizing peripheral circuit size and reducing leakage currents.
Implementation Method 1
a first implantation operation is performed to form a doped region in the semiconductor substrate. A second implantation operation is performed to form a source/drain in the doped region
Implementation Method 2
The semiconductor device may be annealed, for example, using a rapid thermal anneal (RTA) process, to activate the dopants and/or repair radiation damage in the crystal lattice
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a doped region formed in the semiconductor substrate, a source/drain formed in the doped region, a conductive pad formed on the source/drain, a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the conductive pad, a gate formed on the gate dielectric layer, an insulation layer formed over the gate, the gate dielectric layer, and the conductive pad, and a contact formed in the insulation layer in electric contact with the conductive pad.