3D Monolithic Memory Die Interconnect for Low-Z-Height Packaging
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Solution Overview
Problem
Mobile devices with package-on-package (POP) memory face limitations due to wire bonding, which increases cost and z-height, and restricts the number of connections, resulting in lower performance, bandwidth, and higher power consumption.
Innovation Solution
A 3D monolithic memory die is connected face-to-face with an active die using micro-bumps and conductive vias, allowing for a reduced z-height, higher performance, and lower power consumption, while enabling a significant increase in bandwidth through a three-dimensional interconnect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect memory die to active die, then the connection is established, but the z-height increases and cost increases
Solution Approach 1:
The patent transitions from two-dimensional wire bonding connections to three-dimensional vertical interconnects through conductive vias that pass through the memory die substrate. This dimensional change allows direct face-to-face coupling between active die and memory die, eliminating the need for wire bonds and reducing z-height while maintaining connection reliability
2Reliability
If wire bonding is used to connect memory die to active die, then the connection is established, but the cost increases
Solution Approach 1:
The patent merges the connection function with the memory die substrate itself by forming conductive vias directly through the substrate. This integration eliminates separate wire bonding materials and processes, reducing manufacturing cost while maintaining connection reliability through the monolithic structure
3Reliability
If wire bonding is used for interconnection, then connections are established, but the number of connections is restricted resulting in lower bandwidth
Solution Approach 1:
The patent utilizes the third dimension (vertical depth) by forming multiple conductive vias at different depths and positions within the memory die substrate. This enables a significantly higher density of interconnections between active die and memory die, increasing bandwidth by 10x to 100x compared to wire bonding while maintaining connection reliability
Data Source
AI summary
Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.