3D Semiconductor Memory Lower Structure for Defect-Resistant Stacks

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Solution Overview

Problem

Existing semiconductor devices face issues with increased integration density leading to process defects and reduced reliability due to the lamination of gates perpendicular to the substrate surface.

Innovation Solution

A semiconductor device design featuring a substrate structure with a lower structure, upper pattern, stacked structure, vertical structure, and separation structures, where the lower structure includes first and second lower patterns of different materials, and the stacked structure comprises alternating interlayer insulating and gate layers, with specific configurations to prevent defects and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If gates are laminated perpendicular to the substrate surface to improve integration density, then integration density increases, but process defects occur and reliability decreases

Engineering Contradiction:

Improveintegration densityVSAvoiddevice reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The lower structure is divided into multiple patterns (first lower pattern, second lower pattern, third lower pattern) made of different materials, each serving specific functions to prevent defects at different locations where vertical structures pass through the stacked structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different materials are used at different locations of the lower structure: the first lower pattern uses a first material, the second lower pattern uses a second material, and the third lower pattern uses a third material, optimizing local properties where vertical structures intersect with the stacked structure

Inventive Principle:

Principle #3Local quality

2Quantity of substance

If the number of laminated gates increases to improve integration density, then integration density improves, but unexpected process defects occur

Engineering Contradiction:

Improveintegration densityVSAvoidprocess defect rate

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The lower structure with multiple patterns is formed in advance before the stacked structure is assembled, pre-positioning defect-prevention features at locations where vertical structures will pass through, thereby preventing process defects before they occur during subsequent manufacturing steps

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12453090B2Three-dimensional semiconductor memory device

Publication Date: 2025.10.21 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device including a lower structure, an upper pattern, a stacked structure, a separation structure passing through the stacked structure, a vertical structure comprising a channel layer, wherein the stacked structure comprises a plurality of interlayer insulating layers and a plurality of gate layers, the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern, the first lower pattern comprises a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure, and the first lower pattern does not extend toward a side surface of the upper pattern.