3D Semiconductor Memory Erase Structure Using Majority Carriers
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Solution Overview
Problem
The reliability of erase operations in three-dimensional semiconductor memory devices is limited due to the use of gate-induced drain leakage (GIDL) schemes based on minority carriers, which deteriorate the erase operation's effectiveness.
Innovation Solution
A semiconductor memory device with a stack structure including conductive patterns and interlayer insulating layers, a channel layer, a first semiconductor layer with a first impurity type, and a second semiconductor layer with a well region of a different conductivity type, where the channel layer is in direct contact with both layers, enabling an erase operation using majority carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GIDL scheme using minority carriers is used for erase operation, then the erase operation can be performed, but the reliability of the erase operation deteriorates
Solution Approach 1:
The patent changes the fundamental parameter of carrier type used for erase operation from minority carriers (GIDL scheme) to majority carriers. This is achieved by configuring the semiconductor layer with specific doping types (first conductivity type in source/drain regions, second conductivity type in channel region) to enable majority carrier-based erase operations, thereby improving erase reliability
Solution Approach 2:
The patent inverts the conventional approach by using majority carriers instead of minority carriers for the erase operation. The semiconductor layer is configured with opposite doping types compared to traditional designs, allowing the erase operation to proceed through majority carrier mechanisms rather than minority carrier GIDL effects
2Quantity of substance
If three-dimensional memory cell array is implemented, then storage capacity increases, but structural complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory structure to three-dimensional vertical structure by stacking multiple semiconductor layers and conductive patterns in the vertical direction. This enables increased storage capacity by utilizing the third dimension (depth/height) rather than only expanding in the planar direction
Solution Approach 2:
The patent divides the three-dimensional memory structure into multiple discrete semiconductor layers (first semiconductor layer, second semiconductor layer) and conductive patterns stacked alternately with insulating layers. This segmentation allows for modular fabrication and simplifies the manufacturing process by breaking down the complex 3D structure into manageable layers
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a stack structure including conductive patterns and interlayer insulating layers, which are alternately stacked in a first direction; a channel layer penetrating the stack structure; a first semiconductor layer disposed on the stack structure, the first semiconductor layer including a first impurity of a first conductivity type; a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer including a well region with a second impurity of a second conductivity type, wherein the second conductivity type is different from the first conductivity type; and a memory layer between the channel layer and the stack structure.