3D Memory Staircase Marking Pattern for Uniform Etching
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Solution Overview
Problem
The existing fabrication process of 3D memory devices faces challenges due to the loading effect caused by differences in pattern density between the device area and the marking area, leading to uneven etching and reduced precision in trimming rate control of the photoresist layer.
Innovation Solution
A marking pattern is designed with a central marking structure that divides the marking area into sub-areas with equal pattern densities, reducing the loading effect and ensuring more even etching, thereby maintaining the horizontal location of the marking structure and improving precision in trimming rate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a marking pattern is used to control photoresist trimming rate during staircase formation, then the trimming rate control is improved, but the loading effect caused by pattern density differences between device area and marking area causes uneven etching and reduces measurement precision
Solution Approach 1:
The marking area is divided into multiple sub-areas with different pattern densities, where each sub-area has a specific pattern density designed to compensate for the loading effect. The sub-areas are positioned at different distances from the device area, with closer sub-areas having higher pattern densities and farther sub-areas having lower pattern densities, creating a gradient that balances the etching rate across the entire marking area.
Solution Approach 2:
The marking area is segmented into multiple sub-areas, each with distinct pattern densities. This segmentation allows independent optimization of each sub-area's etching characteristics, enabling the overall marking pattern to achieve uniform etching despite the presence of the device area with different pattern density.
2Measurement precision
If the marking area has different pattern density from the device area, then the marking pattern can be used for trimming rate control, but the loading effect causes horizontal shift of the marking structure during etching
Solution Approach 1:
Different sub-areas of the marking pattern have locally optimized pattern densities that compensate for the loading effect gradient caused by the device area. This local optimization ensures that each sub-area experiences a balanced loading effect, preventing the cumulative horizontal shift that would occur with uniform pattern density.
3Ease of manufacture
If a simple marking pattern is used, then the fabrication process is simpler, but the loading effect cannot be compensated and etching uniformity is poor
Solution Approach 1:
The marking area is divided into multiple sub-areas with progressively varying pattern densities. This segmentation approach maintains relative fabrication simplicity while achieving etching uniformity through the systematic variation of pattern density across different sub-areas, avoiding the need for complex asymmetric designs.
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
A semiconductor device includes a stack structure (202) having a plurality of insulating layers and a plurality of conductor layers arranged alternatively over a substrate (201) along a vertical direction. The semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate (201) and neighboring the stack structure (202). The marking pattern includes a central marking structure (206-0) located in a marking area (208), the central marking structure (206-0) dividing the marking area (208) into a first marking sub-area farther from the stack structure (202) and a second marking sub-area closer to the stack structure (202), a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.