3D Memory Mesh Structure Prevents Pattern Collapse

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Solution Overview

Problem

The miniaturization of storage memory cells in planar NAND flash memory is limited by device critical dimensions, hindering the achievement of higher storage capacity and lower costs per bit, necessitating the development of three-dimensional NAND flash memory with multiple planes to meet increasing demand for storage subsystems.

Innovation Solution

A method of forming a three-dimensional memory by creating a stacked structure with alternating semiconductor and insulating layers, patterning a mesh structure, filling dielectric layers in holes, and removing extending parts to form bit line stacked structures, gate pillars, and word lines, which enhances device uniformity and reliability while preventing bending or collapsing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If planar NAND flash memory is used to increase storage capacity, then storage capacity can be increased, but device critical dimension limits further miniaturization

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice critical dimension
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent transitions from planar two-dimensional memory structure to three-dimensional stacked structure with multiple planes. The bit line stacked structures extend in a first direction while word lines extend in a second direction, creating vertical stacking that increases storage capacity without being constrained by planar critical dimensions. This dimensional transition allows continued scaling as device critical dimensions reach physical limits in planar configurations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If high aspect ratio patterns are formed to increase storage density, then storage capacity increases, but bending or collapsing occurs

Engineering Contradiction:
Improvestorage densityVSAvoidstructural stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The mesh structure divides the continuous bit line stacked structure into discrete segments separated by spacers. This segmentation reduces the aspect ratio of individual patterned features while maintaining overall storage density through the three-dimensional array arrangement. The spacers act as support elements that prevent bending or collapsing during fabrication and operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The spacers serve as intermediary support structures between the bit line stacked structures. These spacers provide mechanical support that prevents bending or collapsing of the high aspect ratio patterns while allowing the structures to maintain their intended geometry. The spacers are formed between adjacent bit line stacked structures and extend in the third direction, providing structural reinforcement.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If mesh structure with spacers is formed to prevent bending, then structural stability improves, but device complexity increases

Engineering Contradiction:
Improvestructural stabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The spacers serve multiple functions simultaneously: they provide mechanical support to prevent bending or collapsing, define the spacing between bit line stacked structures, and serve as etch stop layers during fabrication. This multi-functionality reduces the need for additional separate support structures, thereby limiting the increase in device complexity despite the added structural stability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9171862B2Three-dimensional memory and method of forming the same
Publication Date: 2015.10.27 MACRONIX INTERNATIONAL CO LTD
  • US9171862B2 patent drawing
  • US9171862B2 patent drawing
  • US9171862B2 patent drawing

AI summary

A method of forming a three-dimensional memory is provided. A stacked structure including semiconductor layers and insulating layers arranged alternately is formed on a substrate. The stacked structure is patterned to form a mesh structure having first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect with each other. The mesh structure has first holes. A dielectric layer is formed in each first hole. At least a portion of the first strips of the mesh structure is removed to form second holes and bit line stacked structures separated from each other. A charge storage layer is formed on sidewall and bottom of each second hole. A gate pillar extending in a third direction is formed on each charge storage layer in the second hole. Word lines extending in the first direction are formed on the gate pillars.