3D Memory Isolation Layout Using Mesh Hard Mask Pattern
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in achieving higher integration and reduced parasitic capacitance while maintaining efficient memory cell stacking and isolation.
Innovation Solution
A method for fabricating a semiconductor device involving the formation of a stack body with sacrificial layers and hard mask patterns, followed by etching to create isolation openings and filling them with dielectric layers, resulting in a highly integrated 3-D array of memory cells with alternating isolation layers and conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory devices are implemented to increase memory cell density, then memory capacity is improved, but parasitic capacitance increases
Solution Approach 1:
The patent introduces isolation structures (isolation layers and isolation openings) that segment the three-dimensional memory array into distinct regions. These isolation structures electrically isolate adjacent memory cells and conductive lines, preventing capacitive coupling between them. The mesh-shaped hard mask pattern creates a segmented isolation architecture that reduces parasitic capacitance while maintaining high memory cell density in the stacked configuration.
2Quantity of substance
If highly integrated 3-D array is fabricated to increase memory cell density, then manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary sacrificial layers (first and second sacrificial layer structures) that are formed before the final memory cell structures. These sacrificial layers serve as temporary placeholders and etch barriers during fabrication. By removing these sacrificial layers in controlled sequences, the patent enables the formation of complex three-dimensional memory arrays through systematic etching processes, reducing the overall fabrication complexity compared to direct patterning approaches.
Solution Approach 2:
The mesh-shaped hard mask pattern acts as an intermediary etch barrier during the formation of isolation openings. This intermediate mask structure enables precise definition of isolation regions without requiring direct complex patterning of the final isolation structures. The hard mask layer serves as a mediator between the mesh-shaped pattern and the isolation opening formation, simplifying the fabrication process while achieving high integration.
3Ease of manufacture
If conventional etching processes are used to form isolation openings, then manufacturing simplicity is maintained, but manufacturing precision deteriorates
Solution Approach 1:
The patent replaces conventional single-step mechanical etching with a multi-step process that uses a mesh-shaped hard mask pattern as an etch barrier. This substitution enables precise control of isolation opening dimensions and positions. The mesh pattern creates multiple etching barriers that guide the etching process, achieving high manufacturing precision while maintaining relative process simplicity through automated patterning and etching operations.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a stack body including first sacrificial layer structures, preliminary horizontal layers, and second sacrificial layer structures over a lower structure; forming a main hard mask layer over the stack body; forming a mesh-shaped hard mask pattern over the main hard mask layer; forming a main hard mask pattern by etching the main hard mask layer using the mesh-shaped hard mask pattern as an etch barrier; forming a plurality of isolation openings by etching the stack body using the main hard mask pattern as an etch barrier; and forming a plurality of isolation layers that fill the isolation openings.