3D Memory Array Stacking With Metal Bonding for Shorter IC Wiring
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Solution Overview
Problem
Wires in integrated circuits (ICs) dominate performance, functionality, and power consumption as transistor scaling reduces wire performance, necessitating innovative 3D stacking solutions to reduce wire lengths and improve integration.
Innovation Solution
Layer transfer technologies for 3D ICs, including oxide-to-oxide and conductor-to-conductor bonding, enable the construction of multilayer structures with active devices on transferred layers, allowing for heterogeneous integration of memory and logic circuits with thermal isolation and precise alignment techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor scaling is continued to improve performance and density, then transistor performance and density improve, but wire performance degrades
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking by implementing multiple layers of transistors and interconnects stacked in the vertical dimension. This allows continued transistor density improvement through additional stacking layers while maintaining wire performance by keeping lateral wire lengths short within each layer.
Solution Approach 2:
The patent divides the integrated circuit into multiple discrete layers (first layer with transistors, second layer with interconnects, third layer with additional transistors, etc.) that can be independently optimized. Each layer can be designed and fabricated separately then bonded together, allowing wire length optimization in each layer while achieving high overall transistor density.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary fabrication of complete functional layers (transistor layers and interconnect layers) on separate wafers before bonding them together. This allows each layer to be optimized and tested independently, reducing the complexity of managing all layers simultaneously and enabling parallel processing of multiple layers.
Solution Approach 2:
The patent uses bonding interfaces as intermediaries between layers, with specific bonding structures (such as oxide-to-oxide bonding or metal-to-metal bonding) that facilitate controlled joining of layers. These intermediary bonding layers provide mechanical support, electrical connection, and thermal management, simplifying the overall 3D integration process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances IC performance and functionality while reducing development costs and improving yield through efficient 3D stacking with reduced wire lengths and simplified process flows.
Implementation Method 1
the bonding includes oxide to oxide and conductor to conductor bonding
Implementation Method 2
the bonding includes oxide to oxide and conductor to conductor bonding
Data Source
AI summary
A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.