3D Memory Word Line Structure Using Metal Layers and Dual Oxides
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Solution Overview
Problem
Current 3D non-volatile memory devices face challenges in achieving high integration density and data retention due to carrier depletion effects in semiconductor materials used for word line layers, which affect electrical resistivity and memory cell performance.
Innovation Solution
The use of metal materials for word line layers, such as Cu, Al, Ti, and their combinations, which offer lower electrical resistivity and reduce carrier depletion effects, combined with a dual oxide semiconductor layer structure to enhance data retention and stability of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor materials are used for word line layers, then the memory device can be manufactured with conventional processes, but carrier depletion effects occur which increase electrical resistivity and reduce memory cell performance
Solution Approach 1:
The patent changes the material parameter of the word line layers from semiconductor materials to metal materials (such as copper, aluminum, or tungsten). This fundamental material parameter change eliminates carrier depletion effects entirely, as metals do not exhibit this semiconductor phenomenon, thereby reducing electrical resistivity and improving memory cell performance and data retention
Solution Approach 2:
The patent employs a dual oxide semiconductor layer structure consisting of different oxide materials with complementary properties. This composite structure combines the benefits of different materials to achieve both low resistance and high data retention, resolving the contradiction between performance and stability
2Reliability
If metal materials are used for word line layers, then electrical resistivity is reduced and carrier depletion effects are minimized, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter from semiconductor to metal, which fundamentally alters the electrical properties. While this improves resistivity, it requires integrating metal deposition processes (such as sputtering or electroplating) into the existing semiconductor manufacturing flow, adding process steps but enabling superior electrical performance
3Reliability
If single oxide semiconductor layer is used, then manufacturing process is simpler, but data retention and stability are insufficient
Solution Approach 1:
The patent implements a dual oxide semiconductor layer structure where two different oxide materials are stacked together. Each layer contributes different properties - one layer provides low resistance while the other enhances data retention and stability. This composite approach resolves the contradiction by achieving superior reliability through material composition rather than relying on a single material's limitations
Solution Approach 2:
The patent divides the oxide semiconductor structure into two separate layers with distinct functions. This segmentation allows each layer to be optimized for its specific role - one layer for electrical conduction and another for data retention - thereby achieving overall superior performance that a single-layer structure cannot provide
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a faster memory device with improved data retention and stability by reducing poly depletion effects and enhancing carrier transport between electrodes, leading to a more efficient 3D memory array.
Implementation Method 1
metal materials for word line layers, such as Cu, Al, Ti, and their combinations, which offer lower electrical resistivity
Implementation Method 2
enhancing carrier transport between electrodes
Data Source
AI summary
A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.