3D Memory Logic Die Layout With Mixed FinFET and Planar Gate Oxides
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Solution Overview
Problem
Current semiconductor technologies face challenges in efficiently integrating three-dimensional memory arrays with fin field effect transistors and planar field effect transistors, requiring innovative methods for manufacturing semiconductor structures that optimize gate dielectric thickness and transistor design for improved performance.
Innovation Solution
The semiconductor structure comprises a logic die with a word line switching circuit using fin field effect transistors and planar field effect transistors, where the fin field effect transistors have a specific gate dielectric thickness and a method of forming these transistors involves forming semiconductor fins with distinct gate dielectric layers to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single gate dielectric thickness is used for all transistors in the circuit, then the manufacturing process is simpler, but transistor performance cannot be optimized for different circuit requirements
Solution Approach 1:
The patent applies local quality by forming different gate dielectric thicknesses in different regions of the semiconductor device. Specifically, a first gate dielectric layer is formed with a first thickness in a first region, and a second gate dielectric layer is formed with a second thickness in a second region. This allows transistors in different regions to have optimized gate dielectric thicknesses tailored to their specific performance requirements, while maintaining a unified manufacturing process approach.
2Adaptability or versatility
If fin field effect transistors and planar field effect transistors are integrated in the same device, then circuit functionality is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct regions - a first region containing fin field effect transistors and a second region containing planar field effect transistors. Each region is processed independently with region-specific gate dielectric formation, allowing different transistor types to coexist in the same device while maintaining manufacturing precision through localized process control.
Solution Approach 2:
The patent implements local quality by forming gate dielectrics with different thicknesses and structures in different regions. The first gate dielectric layer is formed in the first region for finFETs, and a second gate dielectric layer with different characteristics is formed in the second region for planarFETs. This localized differentiation enables integration of diverse transistor types while maintaining optimal performance for each.
3Reliability
If gate dielectric thickness is optimized for specific transistor regions, then transistor performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies preliminary action by forming a first gate dielectric layer across the entire substrate before selectively removing portions in the second region. This preliminary formation simplifies the manufacturing process by using a sequential approach - first forming a uniform base layer, then selectively modifying specific regions, rather than attempting to form different thicknesses simultaneously in different regions.
Solution Approach 2:
The patent applies the extraction principle by selectively removing a portion of the first gate dielectric layer from the second region after it has been formed. This allows the second region to receive a different gate dielectric structure (the second gate dielectric layer) while the first region retains the original first gate dielectric layer, achieving region-specific optimization through a relatively simple selective removal process.
Data Source
AI summary
A semiconductor structure includes a memory die including a three-dimensional memory device, and a logic die bonded to the memory die. The logic die includes a word line switching circuit containing a fin field effect transistor including a semiconductor fin and a first gate dielectric having a first gate dielectric thickness, and further includes a first additional field effect transistor including a second gate dielectric having a second gate dielectric thickness that is different from the first gate dielectric thickness.