Three-Dimensional Memory Module Stacked With Through Silicon Vias
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Solution Overview
Problem
Computer systems face challenges in increasing main memory performance without corresponding increases in energy consumption or cost, particularly due to the need for long electrical interconnects which lead to higher power consumption and increased costs associated with pin count and die area.
Innovation Solution
The implementation of stacked three-dimensional memory modules using through silicon vias for internal data buses, reducing internal interconnect delays and power consumption, and incorporating an optical layer for high-speed, low-power data transmission through bus waveguides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If electrical interconnects are used to connect memory chips to controller, then data transmission can be achieved, but power consumption increases and signal integrity deteriorates over long distances
Solution Approach 1:
The patent transitions from two-dimensional planar interconnects to three-dimensional vertical interconnects using through-silicon vias (TSVs). Memory stacks are vertically stacked and connected via TSVs that penetrate through the silicon substrate, enabling short vertical connections between layers while eliminating long horizontal wire traces, thus reducing power consumption and improving signal integrity
Solution Approach 2:
The patent replaces electrical interconnects with optical interconnects for data transmission between processor and memory controller. Optical signals transmit through waveguides without suffering from electrical resistance, capacitive loading, and electromagnetic interference that plague electrical wires, thereby reducing power consumption and maintaining signal integrity over longer distances
2Productivity
If the number of DIMM ranks is increased to improve memory capacity, then memory performance improves, but signal timing and noise problems increase due to multi-drop wires
Solution Approach 1:
The patent segments the memory system into multiple independent stacked memory modules, each with its own memory controller. Instead of connecting multiple DIMM ranks through a shared multi-drop bus that suffers from timing and noise issues, each stack operates as an independent unit with dedicated TSV connections, eliminating the Stub electronics problem and maintaining signal integrity while scaling capacity
Solution Approach 2:
The patent moves from horizontal expansion of memory capacity through additional DIMM ranks on the same plane to vertical expansion through stacked memory layers connected by TSVs. This vertical stacking with short direct connections eliminates the long multi-drop wires that cause signal timing and noise problems in traditional horizontal expansions
3Productivity
If front side bus speed is increased to improve memory performance, then bandwidth improves, but interface power consumption increases linearly
Solution Approach 1:
The patent replaces the electrical front-side bus with an optical interconnect system using waveguides and optical signals. Optical transmission does not suffer from the same power consumption constraints as electrical buses, allowing high bandwidth operation without linear increases in interface power consumption, as optical signals can be transmitted over longer distances with lower attenuation and without resistive losses
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed, high-bandwidth interconnects with reduced power consumption and cost, maintaining signal integrity by minimizing wire length and eliminating the need for external electronic connections, thus enhancing scalability and performance.
Implementation Method 1
At least one set of through vias extends approximately perpendicular to a surface of the at least one memory controller through the stack. The vias providing electronic communication between the at least one memory controller and one of the at least one memory layers.
Implementation Method 2
an optical layer... includes at least one bus waveguide configured to transmit data to and from the at least one memory-controller layer
Data Source
AI summary
Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.