3D Semiconductor Memory Device with Mold Structure Support
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the high cost and complexity of forming fine patterns, necessitating the development of three-dimensional semiconductor memory devices with improved design efficiency.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a peripheral circuit structure with stacked electrodes, a mold structure with sacrificial layers, vertical channel structures, and separation insulating patterns to enhance integration density and prevent electrode collapse or leaning during formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor devices are used to achieve high integration density, then manufacturing cost increases due to the need for extremely high-priced apparatuses to form fine patterns
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked electrode structures. This dimensional change allows integration density to increase without requiring extremely fine pattern formation, thereby avoiding the need for extremely high-priced manufacturing apparatuses while achieving high integration density.
2Manufacturing precision
If three-dimensional vertically stacked electrode structures are formed, then integration density increases, but electrode collapse or leaning occurs during formation
Solution Approach 1:
The patent introduces a mold structure with sacrificial layers that is formed beforehand to support the electrode structures during the stacking process. This preliminary support structure prevents electrode collapse or leaning during formation, and the sacrificial layers are later removed to release the final electrode structure with maintained structural stability.
Solution Approach 2:
The mold structure acts as an intermediary element during the electrode formation process. It provides temporary support and defines the electrode geometry during stacking, then is removed after the electrodes are formed, allowing the electrodes to maintain their intended structure without collapse or leaning.
3Adaptability or versatility
If more independent memory blocks are integrated, then device functionality improves, but design complexity increases
Solution Approach 1:
The patent divides the electrode structure into multiple independently controllable stacked electrode structures, each corresponding to separate memory blocks. This segmentation allows each memory block to be independently accessed and controlled, increasing the number of independent memory blocks while the shared peripheral circuit structure maintains design efficiency.
Data Source
AI summary
A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region, a first electrode structure and a second electrode structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern is greater than a maximum width of the separation structure in the second direction.