3D Memory Structure With Monocrystalline Channels for Low Wiring Delay
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Solution Overview
Problem
The scaling of memory technology has slowed, leading to stalled increases in memory capacity and performance, with wires dominating performance and power consumption in integrated circuits, and existing 3D memory structures face challenges in cell performance variations and construction costs.
Innovation Solution
The development of 3D semiconductor devices with monocrystalline channels, utilizing alternating layers of monocrystalline silicon and silicon dioxide, allows for the construction of vertically oriented transistors with shared lithography and etch processes, reducing cell-to-cell performance variations and lowering production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacking of semiconductor devices is implemented, then memory capacity and integration are improved, but wire length reduction leads to decreased wiring delay control
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D stacked architecture, arranging memory cells and transistors in multiple vertical layers. This dimensional change enables higher memory capacity within the same footprint while reducing wire lengths by placing connected components closer together in the vertical dimension, thereby addressing both increased capacity and reduced wiring delay.
2Ease of manufacture
If poly-silicon is used for active memory cell channel, then manufacturing is simplified, but cell-to-cell performance variations increase and drive current decreases
Solution Approach 1:
The patent changes the material parameter of the memory cell channel from poly-silicon to monocrystalline silicon. This parameter change improves cell-to-cell performance consistency and increases drive current due to the superior electrical properties of monocrystalline silicon, while the shared lithography and etch processes maintain manufacturing feasibility through process standardization.
Solution Approach 2:
The patent implements shared lithography and etch processes that serve multiple functions: patterning and forming structures across different layers. This universal approach simplifies manufacturing by using the same equipment and process parameters for multiple purposes, offsetting the increased complexity of monocrystalline silicon fabrication.
3Productivity
If component sizes are scaled down, then transistor performance and density improve, but wire performance degrades and power consumption increases
Solution Approach 1:
The patent employs vertical 3D stacking to achieve higher transistor density without further lateral scaling. By arranging transistors in multiple vertical layers with shared bit lines and word lines, it increases density while reducing wire lengths, thereby lowering wiring delay and power consumption associated with interconnects.
4Adaptability or versatility
If through-silicon via technology is used for 3D stacking, then multiple layers can be constructed separately and bonded, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the fabrication of multiple memory cell layers into a single monolithic structure using shared lithography and etch processes. This combining approach eliminates the need for separate construction and bonding of layers through TSV technology, reducing manufacturing complexity and cost while maintaining the benefits of 3D vertical stacking.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one power down control circuit, and where the device includes a hybrid bonding layer.