3D Memory Multi-Plane Architecture Block Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D memory devices with multi-plane architectures face challenges in efficiently managing memory blocks across different planes, leading to increased power consumption due to the need for simultaneous operations across multiple memory arrays.
Innovation Solution
A 3D memory device architecture that allows independent allocation of addresses to memory blocks across planes, enabling simultaneous access and management of blocks, and utilizes a shared bit line for reduced power consumption during erase verification by charging and discharging operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a composite memory array with multiple planes is used to increase memory cell density, then memory cell integration density is improved, but power consumption increases due to simultaneous operations across multiple memory arrays
Solution Approach 1:
The memory device is divided into multiple independent planes (first plane with first and third mats, second plane with second and fourth mats), each plane containing memory blocks that can be accessed independently. This segmentation allows selective operation of individual planes rather than requiring all planes to operate simultaneously, thereby reducing power consumption while maintaining high memory cell density.
Solution Approach 2:
The patent implements dynamic plane selection capability where the memory system can selectively activate and operate on specific planes based on access requirements. The block management system dynamically determines which plane to access, enabling operations to be conducted on a single plane when possible, thus reducing power consumption while maintaining the capability for high-density storage.
2Quantity of substance
If blocks are distributed across multiple planes in a composite memory array, then memory cell density is improved, but flexibility in managing memory blocks deteriorates due to complex multi-plane operations
Solution Approach 1:
Each plane is designed with identical structural components (mats, bit lines, block structures), making each plane universally interchangeable. The first plane and second plane have the same organizational structure, allowing the memory system to manage blocks across planes using unified protocols and addressing schemes, thereby improving flexibility despite multi-plane distribution.
Solution Approach 2:
The patent organizes memory blocks in a three-dimensional structure with planes stacked vertically, where each plane contains multiple mats. This dimensional organization allows independent addressing of blocks across different planes while maintaining simplified management within each plane, effectively separating the complexity of multi-plane operations into manageable plane-level units.
3Productivity
If simultaneous operations across multiple memory arrays are required, then memory access capability is improved, but power consumption increases
Solution Approach 1:
The memory system segments operations into plane-specific tasks, allowing independent access to first plane or second plane as needed. The bit line sharing arrangement within each plane enables efficient access without requiring simultaneous activation of all planes, thus maintaining productivity while reducing power consumption through selective plane operation.
Solution Approach 2:
The patent implements continuous memory access capability across planes through the stacked architecture, where the first plane and second plane can provide sequential or interleaved access. This continuous access capability maintains high productivity while allowing the system to operate planes in a staggered manner rather than requiring all planes to be active simultaneously, reducing peak power consumption.
Data Source
AI summary
Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.