3D Memory Multi-Tier Moat Isolation Structures
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in effectively isolating memory stack structures and forming reliable interconnections due to limitations in moat isolation structures and interconnection methods.
Innovation Solution
The development of a three-dimensional memory device with multi-tier moat isolation structures, involving alternating stacks of insulating and conductive layers, dielectric moat structures, and through-memory-level interconnection via structures, which includes forming a first-tier alternating stack, a second-tier alternating stack, memory stack structures, dielectric moat structures, and interconnection via structures to enhance isolation and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-tier moat isolation structures are used, then the device structure is simpler, but the isolation efficiency between memory stack structures is insufficient
Solution Approach 1:
The moat isolation structure is divided into multiple tiers (first-tier, second-tier, third-tier moat trenches) with different depths and isolation functions. Each tier segments the isolation task to achieve comprehensive electrical isolation at different vertical levels, resolving the contradiction between isolation efficiency and structural complexity.
Solution Approach 2:
The isolation structure transitions from a single horizontal plane to a multi-level vertical architecture. By adding vertical dimensionality with staggered moat trenches at different depths, the patent achieves three-dimensional isolation that prevents electrical interference while maintaining a manageable structural complexity through systematic layering.
2Productivity
If through-memory-level interconnection via structures are formed, then the interconnection efficiency is improved, but the manufacturing process complexity increases
Solution Approach 1:
Via structures are pre-formed through the alternating stacks before the memory stack structures are completely assembled. This preliminary action allows for optimized placement and connection planning, improving interconnection efficiency while managing manufacturing complexity through staged fabrication processes.
Solution Approach 2:
The via structures are nested within the multi-tier moat isolation architecture, with via holes positioned to connect through multiple isolation tiers. This nesting approach integrates interconnection pathways within the existing isolation structure rather than adding separate interconnection layers, improving efficiency while controlling overall device complexity.
3Quantity of substance
If multi-tier alternating stacks are used, then the memory capacity is increased, but the etching precision requirements are higher
Solution Approach 1:
Different etching processes are applied to different regions and tiers of the alternating stacks. The etching conditions (chemistry, power, pressure) are locally optimized for each tier's specific requirements, allowing high memory capacity through multiple tiers while maintaining achievable etching precision for each individual layer.
Solution Approach 2:
The etching process is segmented into multiple discrete steps, with each step targeting a specific tier or layer interface. This segmentation allows precise control over the depth and profile of each etched feature, enabling the formation of multiple alternating stacks with the required precision without requiring a single complex deep-etch process.
4Reliability
If dielectric moat structures vertically extending through alternating stacks are formed, then the electrical isolation is improved, but the deposition process complexity increases
Solution Approach 1:
The dielectric material deposited in the moat trenches serves multiple functions: electrical isolation between memory stacks, mechanical support for via structures, and definition of isolation boundaries. This multi-functionality improves electrical isolation while reducing deposition process complexity by using a single material system for multiple purposes rather than requiring separate specialized layers.
Data Source
AI summary
A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.