3D Semiconductor Memory Device Multilayer Fabrication
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects, which impact IC performance and power consumption.
Innovation Solution
The development of a method for producing 3D memory devices using a multilayer structure with single crystal layers, through-silicon vias, and antifuse layers to create configurable logic devices, allowing for modular construction of logic, memory, I/O, and analog functions, and reducing the size and number of interconnects through advanced layer transfer techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current semiconductor fabrication methods are used, then manufacturing processes can produce standard IC devices, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The fabrication process is segmented into multiple distinct stages: forming first levels with single crystal layers and transistors, forming second levels with different materials and structures, and selectively bonding specific levels together. This segmentation allows different logic families to be constructed by selecting and bonding appropriate level combinations, providing flexibility without requiring complete new mask sets for each product type.
Solution Approach 2:
The invention transitions from traditional planar 2D IC fabrication to 3D stacked architecture by forming multiple levels vertically stacked above each other. This dimensional change enables greater product diversity and flexibility by combining different functional levels in various configurations, reducing the need for extensive mask set variations while maintaining manufacturing efficiency.
2Reliability
If traditional IC interconnect methods are used, then standard connectivity is achieved, but inter-chip interconnect size and number are large, impacting performance and power consumption
Solution Approach 1:
The invention moves interconnect functionality from the planar 2D domain to the 3D vertical domain by stacking multiple levels with integrated interconnect structures. This allows signal and power distribution to occur through vertical vias and horizontal traces within the stacked architecture, dramatically reducing the number and size of external inter-chip interconnects needed while improving performance and reducing power consumption.
Solution Approach 2:
Multiple functional levels are nested vertically within a compact 3D structure, with each level containing transistors, interconnects, and other circuit elements. This nesting approach consolidates what would traditionally require separate chips and extensive inter-chip bonding into a single integrated 3D device, reducing interconnect complexity while maintaining or improving reliability.
Data Source
AI summary
A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.