3D Semiconductor Memory Fabrication via Multilayer Mask Etching
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Solution Overview
Problem
The high cost of equipment for fine pattern formation in two-dimensional semiconductor manufacturing limits the integration density of semiconductor devices, making it challenging to achieve high performance and low costs.
Innovation Solution
A method for fabricating three-dimensional semiconductor memory devices involves forming a mold structure on a substrate with a multilayered mask layer, including a first mask layer, an etch stop layer, and a second mask layer, which exposes channel regions and non-channel regions, allowing for the formation of channel holes through etching, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fine pattern formation equipment is used in two-dimensional semiconductor manufacturing, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical devices by forming vertical channels extending in the thickness direction of the substrate. This dimensional change allows integration density to increase without requiring progressively more complex fine pattern formation equipment, as the vertical architecture enables higher density through the third dimension rather than through increasingly精细 horizontal patterning
2Quantity of substance
If fine pattern formation equipment is used in two-dimensional semiconductor manufacturing, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
The patent achieves higher integration density by forming three-dimensional vertical memory devices with channels extending through the substrate thickness, rather than increasing horizontal pattern density. This vertical architecture allows multiple memory cells to be stacked in the thickness direction, dramatically increasing the number of devices per chip area without requiring expensive advanced lithography equipment
Solution Approach 2:
The patent divides the substrate into multiple regions with alternating channel regions and non-channel regions, creating a segmented vertical structure. This segmentation allows for the formation of multiple vertical channels in parallel, increasing integration density while using standard manufacturing equipment rather than requiring single increasingly complex patterning steps
Data Source
AI summary
Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.