3D Memory Array Multiple Patterning for Stable High-Aspect Structures
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving optimal aspect ratios for memory cell density without causing structural instability, such as twisting or collapsing of features during the manufacturing process.
Innovation Solution
A multiple-patterning process is employed to form word lines and transistors in a semiconductor memory array, where first and second portions are formed in separate patterning processes, allowing for improved aspect ratios and preventing structural instability by maintaining the aspect ratio within a range that avoids twisting or collapsing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single patterning process is used to form word lines and transistors, then the manufacturing process is simpler, but the aspect ratio cannot be optimized leading to structural instability
Solution Approach 1:
The patterning process is divided into multiple separate patterning operations. First word lines are formed in a first patterning process, then transistors are formed in a second patterning process. This segmentation allows each feature to be optimized independently for aspect ratio while maintaining overall structural stability.
2Productivity
If higher memory cell density is achieved by optimizing aspect ratio, then more cells fit in the array, but structural instability occurs causing twisting or collapsing
Solution Approach 1:
Word lines are formed first as a preliminary structure before forming transistors. The word lines are created with controlled aspect ratios in the first patterning process, establishing a stable framework that prevents subsequent structural instability when transistors are added in the second patterning process.
3Productivity
If aspect ratio is increased to improve memory cell density, then more cells can be packed, but twisting and collapsing of features occurs during manufacturing
Solution Approach 1:
The manufacturing process is segmented into separate patterning steps for word lines and transistors. This allows each feature type to have optimized aspect ratios appropriate for its function, preventing the structural integrity issues that would arise from using a single high aspect ratio for all features.
Solution Approach 2:
Different aspect ratio parameters are used for different features. Word lines are formed with one aspect ratio optimized for their function, while transistors are formed with different dimensions optimized for their function. This parameter differentiation maintains manufacturing precision while improving overall density.
Data Source
AI summary
In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.