3D Memory In-Tier Multiplexer Layout for Smaller Array Footprint
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Solution Overview
Problem
As design rules shrink, less semiconductor space is available for fabricating memory, necessitating a reduction in the footprint and cost of memory cell arrays, particularly in vertical three-dimensional (3D) memory devices.
Innovation Solution
The formation of multiplexer devices in the uppermost tiers of vertically stacked memory cells eliminates the need for additional multiplexer circuitry elsewhere, using a process flow similar to memory cell access devices, with increased doping concentrations for wider source/drain regions and shorter channel lengths to enhance current performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If additional multiplexer circuitry is added outside the memory cell array, then memory cell access control is improved, but the footprint and cost increase
Solution Approach 1:
The multiplexer device is merged with the memory cell array by forming it in the uppermost tier using the same vertical stack structure. This integration eliminates the need for separate multiplexer circuitry outside the array, thereby reducing the overall footprint while maintaining access control functionality.
Solution Approach 2:
The multiplexer device is positioned in the vertical dimension (uppermost tier) rather than being placed in the horizontal plane outside the array. This vertical integration utilizes the third dimension of the 3D memory structure, reducing the horizontal footprint while providing the required access control.
2Reliability
If multiplexer device source/drain width is increased and channel length is decreased, then current performance is improved, but manufacturing complexity increases
Solution Approach 1:
The same fabrication process flow used for forming memory cell access devices is also used for forming the multiplexer device. This universal process approach allows the multiplexer to achieve improved current performance through optimized source/drain width and channel length without requiring separate, more complex manufacturing steps.
Solution Approach 2:
The source/drain regions of the multiplexer device are formed with increased doping concentrations, and the channel length is decreased relative to memory cell access devices. These parameter changes improve current performance while using the same base fabrication process, avoiding additional manufacturing complexity.
Data Source
AI summary
Systems, methods, and apparatus are provided for forming in tier multiplexers in vertical three dimensional (3D) memory. An array of vertically stacked memory cells can include a first isolation region in a storage node region of an array of vertically stacked memory cells, wherein the isolation region is in an uppermost layer of the array of vertically stacked memory cells, and a multiplexer device in a storage node region of the array of vertically stacked memory cells, wherein the multiplexer device is horizontally adjacent to the first isolation region. A digit line contact can be coupled to a first source/drain region of the multiplexer device, and a first digit line can be coupled to a second source/drain region of the multiplexer device.