3D Memory Multi-Stack Contacts for Lithography Misalignment

The patent transitions from planar 2D memory architecture to vertical 3D stacked architecture. Multiple memory stacks are deposited vertically one on top of another, utilizing the third dimension (height) to increase storage density. This dimensional change allows high-density storage while the underlying substrate and via structures maintain electrical connections despite vertical stacking, thereby managing the lithography alignment challenge inherent in multi-stack processes.

The patent implements nested structures where bit lines and source/select lines are formed as interleaved vertical columns that pass through multiple memory stack layers. The conductive structures are nested within the stacked memory layers, with vias connecting corresponding lines across stack boundaries. This nesting approach enables maintaining electrical connectivity while achieving high-density vertical stacking.

The patent applies local quality by creating enlarged nail-like drain/source structures at specific contact points between bit lines and source/select lines. These localized enlarged regions provide reduced contact resistance precisely where BL and SL intersect, while the rest of the device maintains its compact structure. This targeted approach improves read current and speed without requiring complex modifications throughout the entire device.

The patent changes the geometric parameters of the conductive structures by enlarging the cross-sectional area of drain/source regions at contact points. This parameter change (increased area) directly reduces contact resistance according to electrical conduction principles, thereby improving read current and read speed while maintaining overall device simplicity through a straightforward geometric modification.