3D Memory Device N-Type Doped Layer GIDL Body Biasing
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Solution Overview
Problem
The limitations of planar memory cells in terms of density and the challenges faced in scaling them further, as well as the complexities in fabricating 3D memory devices, particularly with issues like residue-dependent sidewall selective epitaxial growth and P-well bulk erase operations, which complicate control of source select gates during read operations.
Innovation Solution
The implementation of a 3D memory device with an N-type doped semiconductor layer in contact with semiconductor channels, allowing for GIDL-assisted body biasing during erase operations and simplifying read operations by eliminating the need for inversion channels, along with a source contact structure design that mitigates gouging variations and overlay control issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and circuit design, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory stack includes multiple levels of word lines, bit lines, and memory cells stacked vertically, enabling significant density improvement without proportionally increasing manufacturing complexity. The 3D structure allows memory cells to be arranged in multiple layers above the substrate, effectively utilizing the vertical dimension to increase storage capacity.
2Manufacturing precision
If sidewall selective epitaxial growth is used in 3D memory fabrication, then channel structure formation is improved, but residue-dependent variations complicate the process control
Solution Approach 1:
The patent removes the problematic residue-dependent sidewall selective epitaxial growth step from the fabrication process. Instead, channel structures are formed by directly depositing semiconductor material into pre-formed holes or trenches that define the channel locations. This extraction of the epitaxial growth step eliminates the residue sensitivity issue while maintaining precise channel structure formation through controlled deposition processes.
Solution Approach 2:
The patent replaces the chemical epitaxial growth mechanism with a physical deposition mechanism. Channel structures are formed by depositing semiconductor material (such as silicon) into defined regions using techniques like chemical vapor deposition (CVD) or atomic layer deposition (ALD), rather than relying on selective epitaxial growth that is sensitive to surface residues. This substitution provides more consistent and controllable channel formation.
3Reliability
If P-well bulk erase operations are used, then erase functionality is achieved, but control of source select gates during read operations becomes complicated
Solution Approach 1:
The patent introduces an N-type doped semiconductor layer specifically at the source contact region, creating a localized doping structure. This N-type layer is positioned between the source contact and the P-type substrate, forming a localized N-type region that facilitates better electrical contact and simplifies source select gate control during read operations. The local quality change in doping type at the source contact interface resolves the control complexity issue while maintaining erase functionality through the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication of 3D memory devices by improving process window and control over source select gates, enabling efficient erase and read operations while avoiding residue-related issues, thus overcoming the limitations of planar memory cells.
Implementation Method 1
allowing for GIDL-assisted body biasing during erase operations
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an N-type doped region of a substrate, an N-type doped semiconductor layer on the N-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region, and a source contact structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region. A first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the memory stack.