3D Memory Multi-Stack Interconnects for Lithography Misalignment
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Solution Overview
Problem
Existing memory devices face challenges in achieving high-density storage without performance degradation due to lithography misalignment, particularly in non-volatile memory devices like ferroelectric random access memory (FeRAM), which affects contact resistance and read speed.
Innovation Solution
A 3D memory system is developed with multiple memory tiers, featuring enlarged nail-like drain/source structures and ferroelectric layers, which improve contact resistance and read speed by optimizing the deposition process to mitigate lithography misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory tiers are stacked to increase storage density, then chip area efficiency and storage capacity improve, but lithography misalignment between tiers increases, leading to degraded contact resistance and read speed
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertical stacking with multiple tiers. Memory strings extend vertically through dielectric layers, allowing multiple memory arrays to be stacked in the vertical dimension. This increases storage density by utilizing the third dimension while maintaining lateral footprint efficiency.
Solution Approach 2:
The patent implements nested structures where conductive elements are positioned within and between memory tiers. Bit lines and source lines are embedded in dielectric layers, with conductive plugs extending through multiple tiers to establish electrical connections. This nested arrangement optimizes space utilization and reduces misalignment sensitivity.
2Ease of manufacture
If conventional deposition processes are used in multi-tier stacking, then manufacturing complexity is reduced, but lithography misalignment causes increased contact resistance
Solution Approach 1:
The patent modifies deposition parameters including temperature, pressure, and material composition to optimize film properties. Dielectric layers are deposited with controlled permittivity and mechanical stress characteristics. Conductive materials are deposited with adjusted composition and crystalline structure to enhance conductivity and reduce contact resistance despite alignment variations.
Solution Approach 2:
The patent employs composite material structures combining different dielectric materials with complementary properties. Multiple dielectric layers with varying permittivity and stress characteristics are stacked to achieve optimal electrical and mechanical performance. Conductive plugs use composite material compositions to balance conductivity, adhesion, and tolerance to misalignment.
3Quantity of substance
If memory strings are closely spaced to increase density, then storage capacity improves, but read current and signal integrity deteriorate
Solution Approach 1:
The patent applies local quality optimization by varying material properties and structural dimensions in different regions. Dielectric layer thicknesses and compositions are locally adjusted between closely spaced memory strings to maintain electrical isolation. Conductive plug dimensions are optimized locally to enhance current carrying capacity while minimizing interference between adjacent strings.
Solution Approach 2:
The patent introduces dielectric intermediary layers between closely spaced memory strings to provide electrical isolation and mechanical support. These intermediary dielectric structures prevent signal crosstalk while maintaining close spacing for high density. Conductive plug structures act as intermediaries to efficiently transfer read current from memory cells to bit lines.
Data Source
AI summary
A memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.