3D Charge-Trap Memory with Negative Capacitance Channel Structure

The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory array is arranged in multiple stacked layers with word lines extending in first and second directions, and bit lines connecting to memory cells across different layers. This vertical stacking approach increases memory density without requiring further reduction of feature sizes, thereby avoiding the manufacturing complexity and cost issues associated with continued planar scaling.

By stacking memory layers vertically in the third dimension, the patent achieves increased memory density without requiring further reduction of lateral feature sizes. The word lines and bit lines are configured to extend across multiple layers, with connection structures (such as contact plugs and via holes) providing vertical interconnections. This approach maintains manufacturable feature sizes while achieving higher density through architectural innovation rather than continued miniaturization.

The patent implements control gate structures that extend in both first and second directions to control memory cells across multiple stacked layers. Word lines extend in the first direction and bit lines extend in the second direction, with control gates positioned to control access to memory cells in different layers. While this creates a more complex control structure compared to planar architecture, it enables significantly higher memory density through vertical stacking, making the complexity worthwhile for achieving the upper density limits that planar scaling cannot provide.