3D Memory Cell Stack With Nested Bit Line and Comb Word Line
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration density due to the need for expensive processing equipment to form fine patterns, and three-dimensional devices aim to overcome these limitations by stacking memory cells vertically, but require innovative architectures to enhance electrical properties and integration.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure comprising vertically stacked layers, including word lines, channel layers, and data storage elements, where the word line has a comb shape with gate electrodes protruding and a bit line is electrically connected to the channel layer, allowing for increased integration and improved electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern formation techniques to increase integration density, then integration density improves, but manufacturing cost increases due to expensive processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking, where multiple memory cells are stacked along the vertical direction. This dimensional change allows integration density to increase without requiring finer lateral patterning, thereby avoiding the need for expensive processing equipment while achieving higher capacity
2Quantity of substance
If three-dimensional semiconductor memory devices stack memory cells vertically to increase integration, then integration density improves, but electrical properties deteriorate due to increased resistance and capacitance in vertical interconnects
Solution Approach 1:
The patent implements a nested structure where bit lines are formed within hollow channels of the channel layer, and word lines with gate electrodes are positioned within recesses of the stack. This nesting arrangement shortens the vertical distance between intersecting word and bit lines, reducing interconnect resistance and capacitance, thereby improving electrical properties while maintaining high integration density
Solution Approach 2:
The patent segments the word line into a first conductive line and protruding gate electrodes, creating a comb-shaped structure. This segmentation allows the bit line to intersect multiple gate electrodes at different horizontal positions, reducing the vertical interconnect length and improving electrical characteristics
Data Source
AI summary
A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.