3D Memory Array Layout for Neuromorphic Multiply-Accumulate
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Solution Overview
Problem
Performing a large number of multiply-accumulation operations in neuromorphic computing devices is computationally exhaustive and consumes significant hardware resources, leading to high power consumption and reduced operating speed due to the need for complex logic circuits and long routing metal rails.
Innovation Solution
A three-dimensional memory array is used to store weight values of a neural network model, allowing for multiply-accumulation operations without complex logic circuits, and is stacked above a controller to reduce the length of routing metal rails, thereby enhancing power efficiency and operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex logic circuits are used to perform multiply-accumulation operations, then computation capability is improved, but power consumption increases and operating speed decreases
Solution Approach 1:
The patent replaces complex logic circuits with a memory array that performs multiply-accumulation operations through inherent electrical properties. The memory array uses conductive paths and resistive elements to naturally perform multiplication and accumulation of neural network weights and inputs, eliminating the need for traditional logic circuits and significantly reducing power consumption while maintaining computation capability
Solution Approach 2:
The patent transitions from two-dimensional planar logic circuit layout to three-dimensional stacked memory array architecture. By stacking memory cells vertically, the system achieves higher density and shorter routing paths, enabling efficient parallel processing of neural network computations with reduced power consumption and improved operating speed
2Productivity
If complex logic circuits are used to perform multiply-accumulation operations, then computation capability is improved, but device complexity increases
Solution Approach 1:
The memory array is designed to serve dual purposes: storing neural network weights and performing compute operations. The same memory cells that store weight values also perform multiplication and accumulation when voltage signals are applied, eliminating the need for separate logic circuitry and reducing overall device complexity while maintaining computation capability
Solution Approach 2:
The memory array inherently performs multiply-accumulation operations through its electrical characteristics without requiring external logic circuits. The conductive paths and resistive elements naturally execute the mathematical operations when voltage signals representing neural network inputs are applied, making the memory structure self-sufficient for both storage and computation
3Area of stationary object
If long routing metal rails are used to connect memory and controller, then area coverage is improved, but parasitic components increase and operating speed decreases
Solution Approach 1:
The patent stacks the memory array vertically above the controller in three dimensions, transforming the traditional two-dimensional lateral routing into vertical interconnections. This stacking architecture dramatically reduces the length of routing metal rails and minimizes parasitic resistance and capacitance, enabling faster signal transmission while still covering the required functional area
Solution Approach 2:
The memory array is positioned directly above the controller in a nested vertical arrangement, with the controller layer at the bottom and memory layers stacked above. This nested configuration minimizes the distance between components and reduces routing path lengths, improving operating speed while efficiently utilizing the available device area
4Area of stationary object
If long routing metal rails are used to connect memory and controller, then area coverage is improved, but power consumption increases
Solution Approach 1:
The vertical stacking architecture transforms long lateral routing paths into short vertical interconnections, dramatically reducing the length of metal rails. This dimensional change reduces parasitic resistance and capacitance, thereby lowering the power consumption required for signal transmission while maintaining adequate area coverage for both memory and controller functions
Data Source
AI summary
Disclosed herein are related to a device for performing neuromorphic computing. In one aspect, a device includes a back end of line layer including a three-dimensional memory array. The three-dimensional memory array may include a plurality of memory cells to store a plurality sets of weight values of a neural network model. In one aspect, the device includes a front end of line layer including a controller. The controller may apply one or more input voltages corresponding to an input to the neural network model to the three-dimensional memory array, and receive one or more output voltages from the three-dimensional memory array to perform computations of the neural network model.