3D Memory Stacks With Silicon Nitride Dielectrics for Uniform Isolation
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Solution Overview
Problem
3D memory devices face challenges in scaling up due to thermal budget differences between upper and lower decks, leading to nonuniform silicon oxide gate-to-gate dielectric layers, which result in reduced production yield and electrical performance.
Innovation Solution
The use of non-silicon oxide gate-to-gate dielectric layers, such as silicon nitride or silicon oxynitride, which have higher dielectric constants and improved barrier performance, reducing gate-to-gate coupling and leakage, and are formed using alternating polysilicon and silicon nitride layers with controlled oxidation to create composite layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide gate-to-gate dielectric layers are used in 3D memory devices, then the manufacturing process is simpler and cost-effective, but the dielectric quality becomes nonuniform due to thermal budget differences between upper and lower decks, reducing production yield and electrical performance
Solution Approach 1:
The patent changes the material parameter from silicon oxide to silicon nitride for the gate-to-gate dielectric layer. Silicon nitride has inherently better thermal stability and maintains uniform dielectric properties across different thermal budgets, resolving the uniformity issue while remaining manufacturable through standard CVD processes
Solution Approach 2:
The patent employs a composite dielectric structure consisting of multiple layers including silicon nitride gate-to-gate dielectric layers combined with tunnel dielectric layers and blocking dielectric layers. This composite approach allows each layer to be optimized for its specific function while maintaining overall structural uniformity across the 3D memory stack
2Ease of manufacture
If silicon oxide gate-to-gate dielectric layers are used, then the fabrication process is easier, but gate-to-gate coupling and leakage increase due to lower dielectric constant and barrier performance
Solution Approach 1:
The patent changes the dielectric material parameter from silicon oxide (lower dielectric constant) to silicon nitride (higher dielectric constant of approximately 7.5). This parameter change provides superior electrical isolation between gates, reducing gate-to-gate coupling and leakage while maintaining compatibility with existing fabrication processes
Solution Approach 2:
The patent uses silicon nitride which can be deposited using standard chemical vapor deposition (CVD) processes that are already widely available in semiconductor manufacturing. This approach provides high-performance dielectric properties without requiring expensive or complex additional fabrication equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the production yield and electrical performance of 3D memory devices by maintaining better dielectric quality across the memory stack, reducing thermal budget-induced losses and improving barrier performance.
Implementation Method 1
A plurality of doped polysilicon layers and a plurality of silicon nitride layers are alternatingly deposited above a substrate
Implementation Method 2
formed using alternating polysilicon and silicon nitride layers with controlled oxidation to create composite layers
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. a memory stack including a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above a substrate is formed. Each of the gate-to-gate dielectric layers includes a silicon nitride layer. A NAND memory string extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack is formed. A slit structure extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack is formed.