3D Ferroelectric Memory Cell Layout for Noise and Ioff Isolation
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, issues such as cell-to-cell noise interference and off current (Ioff) leakage become significant challenges, affecting the performance and reliability of memory devices.
Innovation Solution
A 3D ferroelectric memory device is developed with vertically stacked memory cells, each comprising a word line, bit line, and source line, utilizing a ferroelectric material as a gate dielectric and an oxide semiconductor channel layer, which is segmented to reduce noise interference and enhance the Ion/Ioff ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but cell-to-cell noise interference and off current leakage increase
Solution Approach 1:
The channel layer is segmented into multiple independent channel segments, each corresponding to a specific memory cell. This segmentation electrically isolates adjacent memory cells, preventing noise interference and off current leakage between cells while maintaining high integration density through the 3D stacked architecture.
Solution Approach 2:
The patent transitions from a planar 2D memory structure to a 3D stacked structure with vertically arranged memory cells. This dimensional change increases integration density by utilizing the vertical space, and when combined with channel segmentation, effectively isolates cells to reduce noise and off current issues.
2Ease of manufacture
If continuous channel layer is used to simplify manufacturing, then fabrication process is easier, but cell-to-cell noise interference and off current leakage occur
Solution Approach 1:
The channel layer is divided into multiple channel segments with insulating material positioned between them. This segmentation can be achieved through selective etching processes that remove portions of the channel layer between adjacent memory cells, providing electrical isolation while maintaining compatibility with standard semiconductor fabrication techniques.
Solution Approach 2:
Portions of the channel layer are selectively removed (taken out) between adjacent memory cells to create isolated channel segments. This extraction of channel material between cells provides the necessary electrical isolation to prevent noise and off current while preserving the continuous channel structure within each individual cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration significantly reduces cell-to-cell noise interference and off current, enhancing the Ion/Ioff ratio, thereby improving the performance and reliability of the memory device.
Implementation Method 1
a ferroelectric layer (90) disposed between the channel segments (92A-92D) and the conductive layers (72A-72D), respectively
Data Source
AI summary
A device includes a multi-layer stack, a plurality of channel segments and a ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel segments are disposed on sidewalls of the conductive layers, separately and respectively. The ferroelectric layer is disposed between the channel segments and the conductive layers, respectively.