3D Memory Device With Non-Overlapping Electrode Pads
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Solution Overview
Problem
The integration of two-dimensional memory devices is limited by the need for expensive equipment for fine pattern formation, and three-dimensional memory devices face challenges in reducing size and improving reliability while increasing the stack number of electrode layers.
Innovation Solution
A three-dimensional memory device with an electrode structure featuring alternately stacked interlayer dielectric and electrode layers, including a pad part that does not overlap with other electrode layers, and a method for manufacturing this device involving the formation of a pre-stack, step structure, contact holes, and replacement of sacrificial layers with conductive material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stack number of electrode layers is increased to improve integration degree, then the degree of integration is improved, but the device size and complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory device layout to three-dimensional stacked electrode layers. Multiple electrode layers are arranged vertically in the third dimension, allowing increased integration degree without proportionally increasing the planar layout area. This dimensional change enables higher capacity while managing device complexity through vertical stacking rather than horizontal expansion.
2Productivity
If the stack number of electrode layers is increased to improve integration degree, then the degree of integration is improved, but the device size increases
Solution Approach 1:
The patent implements nested stacking where multiple electrode layers are vertically arranged within a compact footprint. Each electrode layer is nested above the previous one, similar to nested dolls, allowing the device to achieve high integration degree while maintaining a compact overall volume. The vertical stacking enables more storage capacity within the same or reduced device footprint compared to planar arrangements.
Data Source
AI summary
A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor.