3D-Stacked Memory Chip Layout for Dense NPU Integration

The patent transitions from a two-dimensional planar layout to a three-dimensional vertical stacking architecture. Multiple chip layers (first chip layer, second chip layer, third chip layer) are stacked vertically and interconnected through through-silicon vias (TSVs), enabling significantly higher integration density without increasing the lateral chip footprint. This dimensional change allows circuits to be arranged in multiple levels rather than competing for the same planar space.

The patent divides the integrated circuit into multiple separate chip layers, each containing specific functional blocks (e.g., memory cells in first chip layer, logic circuits in second chip layer, I/O interfaces in third chip layer). This segmentation distributes the heat-generating circuits across multiple physically separated layers, improving thermal management by reducing heat concentration in any single location while maintaining high overall integration density.

The patent implements a nested structure where multiple chip layers are stacked and interconnected through through-silicon vias (TSVs) that penetrate through the chip layers. Each chip layer contains functional blocks that are nested within the overall three-dimensional structure, with TSVs providing vertical interconnections between layers. This nested architecture achieves high integration density while using standardized semiconductor manufacturing processes for TSV formation and chip stacking.

The patent uses vertical stacking with through-silicon vias to create short interconnect paths between functional blocks located in different chip layers. Data can be transmitted vertically between layers through TSVs, minimizing the transmission distance compared to lateral routing in planar designs. This three-dimensional interconnection approach reduces signal propagation delay and improves processing speed while managing the design complexity through systematic layer assignment and TSV placement.