3D Semiconductor Memory Structure With Offset Sidewalls
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the high cost and complexity of equipment needed for fine pattern formation, making it difficult to increase their integration density, which is essential for meeting customer demands for high-performance and low-cost semiconductor devices.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a structure that includes a second substrate on a first substrate, featuring a vertical channel structure, interlayer dielectric layer, and cutting structure to increase integration density, along with a method of fabricating this device by forming stacked electrodes, sacrificial layers, and through contacts to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional semiconductor devices are used with fine pattern formation, then device performance is improved, but manufacturing cost and equipment complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory devices. Multiple memory cell layers are stacked vertically on a single substrate, with word lines extending in the first direction and bit lines in the second direction, creating a three-dimensional architecture that increases integration density without requiring proportionally more complex manufacturing equipment
2Reliability
If two-dimensional semiconductor devices are used with fine pattern formation, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
By stacking multiple memory cell layers vertically, the patent achieves higher integration density and performance without proportionally increasing manufacturing cost. The three-dimensional structure allows more memory cells to be formed on a single substrate using standard fabrication processes, reducing the cost per bit compared to two-dimensional scaling
Solution Approach 2:
The memory device is divided into multiple stacked memory cell layers, each containing memory cells formed by the intersection of word lines and bit lines. This segmentation allows the manufacturing process to be applied repeatedly in the vertical direction, increasing capacity without requiring proportionally more complex or expensive manufacturing steps
3Quantity of substance
If integration density is increased in two-dimensional devices, then more memory cells are achieved, but the area occupied by each unit memory cell must be reduced
Solution Approach 1:
The patent increases integration density by stacking multiple memory cell layers vertically rather than packing more cells horizontally. Each memory cell layer contains memory cells formed at the intersection of word lines extending in the first direction and bit lines extending in the second direction, with vertical channel structures penetrating through the stacked layers, effectively utilizing the third dimension to increase capacity without reducing unit cell area
4Quantity of substance
If three-dimensional stacked structure is implemented, then integration density is increased, but device structure complexity increases
Solution Approach 1:
The patent implements a three-dimensional stacked structure with multiple memory cell layers, where each layer contains memory cells formed by intersecting word lines and bit lines. Vertical channel structures penetrate through the stacked layers to connect memory cells across different levels. While the structure is three-dimensional, the regular stacking pattern and systematic arrangement of components maintain manufacturing feasibility and device reliability
Data Source
AI summary
Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.