3D Semiconductor Memory Device With Oxide-to-Oxide Wafer Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through Silicon Via (TSV) sizes, which restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to construct configurable logic, allowing for multiple layers of single crystal transistors with oxide-to-oxide bonds and incorporating memory cells, and a refresh control circuit, enabling efficient power distribution and interconnects through layer transfer techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent segments the fabrication process into modular stages using wafer bonding, where separate wafers are processed independently and then bonded together. This allows different product configurations to be achieved by recombining standardized modules, reducing the need for complete mask set redesigns and lowering costs while improving flexibility.
Solution Approach 2:
The patent enables dynamic reconfiguration of semiconductor products through wafer bonding techniques that allow post-fabrication modification. Products can be reconfigured by bonding different wafer combinations, allowing the manufacturing system to adapt to diverse product requirements without requiring complete process redesign, thus improving flexibility while maintaining manufacturing efficiency.
2Productivity
If Through Silicon Via (TSV) technology is used in 3D IC, then vertical interconnect is achieved, but TSV size is large which restricts number of connections
Solution Approach 1:
The patent transitions from planar 2D interconnect patterns to 3D vertical interconnect structures using wafer bonding and TSV technology. By adding the vertical dimension, the system achieves higher connection density without increasing lateral TSV size, allowing more connections to be made through the third dimension while maintaining manageable TSV dimensions.
Solution Approach 2:
The patent implements nested interconnect structures where multiple interconnect levels are stacked vertically through wafer bonding. Multiple TSV layers are nested within each other at different vertical levels, allowing numerous connections to be packed into a compact volume without requiring each individual TSV to be oversized, thus increasing connection count while controlling TSV size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing the need for multiple mask sets and increases the density of connections in 3D ICs, enabling more complex and flexible semiconductor devices with improved performance and power management.
Implementation Method 1
the bonded includes oxide to oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).