3D Memory Oxide Structure for Lower Series Resistance
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Solution Overview
Problem
In three-dimensional memory cell arrays, the increased series resistance between stacked memory elements leads to current loss and heat generation, and the interface between semiconductor and insulator can form trap centers, affecting transistor performance.
Innovation Solution
A semiconductor device structure with a specific oxide layer configuration and nitride layers is introduced, where the oxide layers have different resistance regions and are strategically positioned to reduce series resistance and suppress trap center formation, including a method for manufacturing such devices with heat treatment and precise layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity increases, but series resistance between memory cells increases
Solution Approach 1:
The patent applies local quality by creating a nitride layer specifically at the interface between the semiconductor pattern and insulator, and by forming low-resistance oxide regions at specific locations within the stacked memory cell structure. This localized treatment reduces series resistance at critical interfaces without affecting the overall stacking architecture, thereby maintaining high storage capacity while improving electrical characteristics.
2Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity increases, but heat generation in the memory cell array increases
Solution Approach 1:
The patent introduces low-resistance oxide regions and nitride layers at specific interfaces within the stacked memory cell structure. By locally reducing resistance at these critical points, the overall power consumption and heat generation in the memory cell array is reduced, enabling high-density stacking without excessive heat accumulation.
3Reliability
If semiconductor pattern contacts insulator to form trap centers, then threshold voltage shifts in positive direction, but on-state current and reliability deteriorate
Solution Approach 1:
The patent introduces a nitride layer as an intermediary between the semiconductor pattern and the insulator. This intermediate layer prevents direct contact that would otherwise create trap centers, thereby maintaining low on-state current and high reliability while still allowing the semiconductor to function properly with the insulator.
4Reliability
If series resistance is reduced by modifying oxide regions, then electrical characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent modifies the resistance parameters of oxide regions by controlling their formation conditions and composition. By adjusting the resistance of specific oxide regions during manufacturing, the patent achieves improved electrical characteristics without requiring complex additional processing steps, as the resistance control is integrated into the existing fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces series resistance, enhances current flow, and improves reliability by minimizing trap center formation, leading to improved electrical characteristics and increased storage capacity per unit area.
Implementation Method 1
The oxide includes a first region in the first opening, a second region in the second opening, and a third region in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
Implementation Method 2
A semiconductor device structure with a specific oxide layer configuration and nitride layers is introduced, where the oxide layers have different resistance regions and are strategically positioned to reduce series resistance and suppress trap center formation, including a method for manufacturing such devices with heat treatment and precise layer formation.
Data Source
AI summary
A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.