3D Memory Electrode Pad Structure for Dense Reliable Contacts
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Solution Overview
Problem
The challenge is to enhance the integration density and reliability of semiconductor devices while overcoming the limitations of expensive process equipment required for fine pattern formation in two-dimensional or planar semiconductor devices.
Innovation Solution
The semiconductor device is configured with a substrate having a cell array region and a connection region, featuring an electrode structure with stacked electrodes, vertical patterns, a cell contact, and an insulating pillar. The pad portion of the electrode includes a first portion with a top surface higher than the line portion and a second portion with a protruding portion covering the insulating pillar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices use fine pattern forming technology to increase integration, then integration density is improved, but process equipment cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, with each layer containing memory cells formed by intersecting word lines and bit lines. This dimensional change allows integration density to increase without requiring finer pattern formation, thereby avoiding the need for expensive advanced lithography equipment.
2Quantity of substance
If three-dimensional semiconductor memory devices are designed to increase integration density, then integration is improved, but device complexity increases
Solution Approach 1:
The three-dimensional memory device is segmented into multiple identical memory cell layers stacked vertically. Each layer contains the same basic structure of word lines, bit lines, and memory cells, creating a modular architecture. This segmentation allows the complex three-dimensional structure to be built by repeating a standardized unit cell design, simplifying the overall device design and manufacturing process.
Solution Approach 2:
Multiple memory cell layers are nested vertically, with each layer containing memory cells formed by the intersection of word lines and bit lines. The nested structure allows compact three-dimensional integration while maintaining the simplicity of two-dimensional cell design within each layer, effectively managing device complexity through hierarchical organization.
Data Source
AI summary
A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.