3D Memory Cell Pad Structure for Vertical Interconnect Speed
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Solution Overview
Problem
Existing three-dimensional semiconductor devices face challenges in achieving high integration and fast operating speed due to limitations in stacking memory cells and forming efficient conductive structures.
Innovation Solution
A semiconductor device is designed with a vertical conductive line, dielectric pad layer, and horizontal conductive line stacks, along with edge slits and supporting elements, using materials like silicon oxide and silicon nitride to enhance integration and speed through a manufacturing process involving sacrificial layers and oxidation/deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three-dimensional arrangements to increase integration, then device complexity increases, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The device is divided into multiple stacked memory cell layers, each independently formed through sequential deposition and etching cycles. This segmentation allows precise control of each layer's thickness and position, maintaining manufacturing precision while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. By utilizing the vertical dimension, the device achieves higher integration density without compromising manufacturing precision, as each layer can be independently fabricated with controlled thickness and alignment.
2Speed
If conventional conductive structures are used in three-dimensional memory devices, then device complexity is reduced, but operating speed deteriorates
Solution Approach 1:
The patent introduces vertical conductive lines that extend through multiple memory cell layers, enabling direct vertical signal transmission. This three-dimensional conductive architecture reduces signal path length and resistance compared to conventional planar structures, improving operating speed despite increased structural complexity.
Solution Approach 2:
Horizontal conductive lines are embedded within the vertical stack of memory cells, with conductive lines nested between alternating semiconductor layers. This nested arrangement creates efficient conductive pathways that penetrate through multiple functional layers, enhancing signal transmission speed while integrating seamlessly into the three-dimensional memory structure.
3Manufacturing precision
If sacrificial layers are used to form air gaps and improve connectivity, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Sacrificial layers are deposited between the semiconductor layers during the initial stacking process, before the final memory cell structure is complete. These preliminary sacrificial structures define the future air gap positions and enable precise control of conductor placement, improving manufacturing precision while the additional process steps increase device complexity.
Solution Approach 2:
The sacrificial layers serve as intermediary structures that temporarily occupy space during fabrication, guiding the formation of air gaps and conductive pathways. These intermediary elements enable precise positioning of critical features through controlled removal, achieving high manufacturing precision despite the added complexity of the sacrificial layer deposition and removal processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high integration and fast operating speed by forming efficient conductive structures, allowing for improved stacking and connectivity of memory cells.
Implementation Method 1
forming a dielectric pad layer that fills the air gap
Implementation Method 2
The forming of the dielectric pad layer comprises an oxidation process or a deposition process
Data Source
AI summary
A semiconductor device may include a peripheral circuit portion, a memory cell array disposed over the peripheral circuit portion and including a vertical conductive line, a bonding pad structure between the peripheral circuit portion and the memory cell array, a dielectric pad layer configured to cover the top of the vertical conductive line of the memory cell array, and a higher-level pad that is coupled to the vertical conductive line through the dielectric pad layer.