3D Memory Pad Structure With Stepped Openings for Lower RC Delay
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Solution Overview
Problem
As two-dimensional non-volatile memory devices approach their physical scaling limits, there is a need for improved manufacturing methods and structures to enhance the reliability and efficiency of three-dimensional non-volatile memory devices, particularly in reducing the distance between circuitry and cell structures to increase program speed and integration density.
Innovation Solution
The semiconductor device incorporates a pad structure with stepped layers and openings that electrically couple pads to cell structures, reducing the distance between circuitry and cell structures, and employing a manufacturing method that forms stacked structures with patterned and non-patterned regions to simplify the process and enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional two-dimensional memory device structure is used, then the manufacturing process is simpler, but the integration density and program speed are limited due to physical scaling limits
Solution Approach 1:
The patent transitions from a two-dimensional memory device structure to a three-dimensional structure by stacking multiple cell structures vertically. The memory device includes first and second cell structures stacked on a substrate, with pad structures connecting to both cells at different heights, thereby increasing integration density by utilizing the vertical dimension.
2Speed
If the distance between circuitry and cell structures is increased, then the pad area is larger, but the program speed and RC delay performance deteriorate
Solution Approach 1:
The pad structure extends vertically to connect to both first and second cell structures at different heights, reducing the horizontal distance and RC delay between the pad and cell structures while minimizing the pad area footprint on the substrate.
Solution Approach 2:
The pad structure is configured with different regions at different heights, where the first pad connects to the first cell structure and the second pad connects to the second cell structure, optimizing the local connection quality and minimizing distance to each respective cell.
3Reliability
If multiple separate pad structures are used to connect to stacked cell structures, then the electrical coupling is more complex, but the manufacturing process becomes more complicated
Solution Approach 1:
The pad structure is formed as a single integrated structure that simultaneously connects to both first and second cell structures through its vertical extension, rather than using separate pad structures for each cell, thereby simplifying the manufacturing process while maintaining reliable electrical coupling.
Solution Approach 2:
The pad structure serves multiple functions: it connects to both first and second cell structures, provides electrical coupling for multiple memory cells, and acts as a common interface for read/write operations, thereby simplifying the overall device architecture.
Data Source
AI summary
A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.