3D Memory Page Buffer Sensing for Faster Hard/Soft Reads

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Solution Overview

Problem

Existing memory technologies face challenges in efficiently distinguishing and reading multiple memory states in three-dimensional memory devices due to the small channel current, which complicates direct measurement and prolongs reading times.

Innovation Solution

A method involving a read operation using multiple read voltages to obtain hard and soft read values, storing these values and inhibition information in latches, and employing a page buffer with a master latch and data latches to manage and release data efficiently, reducing sensing times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple read voltages are applied to distinguish multiple memory states in three-dimensional memory devices, then measurement precision is improved, but reading time is prolonged

Engineering Contradiction:
Improvedistinguishing accuracy of memory statesVSAvoidreading time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a first sensing operation to obtain hard read values before performing a second sensing operation to obtain soft read values. This preliminary classification allows the system to quickly identify memory states that can be clearly distinguished (hard data) and separate them from those requiring more detailed analysis (soft data), thereby reducing the total sensing time while maintaining measurement precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the reading process into two distinct phases: hard data sensing and soft data sensing. By dividing the memory states into those that can be reliably read with shorter sensing times and those requiring longer sensing times, the system can process different types of data through optimized pathways, improving overall reading efficiency without sacrificing accuracy.

Inventive Principle:
Principle #1Segmentation

2Productivity

If sensing time is reduced to improve reading speed, then productivity is improved, but measurement precision deteriorates

Engineering Contradiction:
Improvereading speedVSAvoiddistinguishing accuracy of memory states
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies partial action by performing two sequential sensing operations with different durations. The first sensing operation uses a shorter duration to obtain hard read values for quick identification, while the second sensing operation uses a longer duration to obtain soft read values for accurate distinction of difficult-to-read states. This partial application of extended sensing time only where necessary maintains productivity while ensuring measurement precision.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If multiple latches are used to store hard read values, soft read values, and inhibition information, then device complexity is increased, but ease of operation is improved

Engineering Contradiction:
Improvedata management efficiencyVSAvoidnumber of latches in page buffer
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent applies universality by designing latches that can store multiple types of information (hard read values, soft read values, and inhibition information) through different configurations and timing sequences. The same latch structure serves multiple functions by storing different data types at different times and releasing them in appropriate sequences, reducing the need for separate dedicated storage elements for each data type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250341982A1Method of controlling memory, memory and memory system
Publication Date: 2025.11.06 YANGTZE MEMORY TECH CO LTD
  • US20250341982A1 patent drawing
  • US20250341982A1 patent drawing
  • US20250341982A1 patent drawing

AI summary

According to one aspect of the present disclosure, a method of controlling a memory is provided. The method may include performing a read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page. The method may include storing the hard read value, the soft read value, and inhibition information into three latches in a page buffer, respectively. The method may include obtaining hard data of the target logical page based on the hard read value of the target logical page. The method may include obtaining soft data of the target logical page based on the hard data and the soft read value of the target logical page. The memory may include a plurality of memory cells, each configured to store N-bit data, where N is an integer greater than 1.