3D Ferroelectric Memory Cell Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for higher integration density, challenges arise in integrating three-dimensional memory devices with ferroelectric materials, such as parasitic capacitance and energy consumption bottlenecks due to off-chip memory access.
Innovation Solution
The formation of a three-dimensional memory device involves creating a layer stack with dielectric, channel, and source/drain layers, forming openings, lining sidewalls with a ferroelectric material, and constructing gate electrodes using conductive materials, which reduces parasitic capacitance and allows for high-density memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional memory devices are integrated with higher density, then integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertically stacked memory cells. Multiple memory layers are stacked vertically with gate electrodes extending through multiple layers, enabling higher integration density while maintaining controlled parasitic capacitance through the vertical architecture.
Solution Approach 2:
The memory device is divided into multiple discrete layers including first and second memory layers, each with distinct gate electrodes, channel layers, and dielectric layers. This segmentation allows independent optimization of each layer and reduces inter-layer parasitic capacitance through strategic dielectric placement.
2Productivity
If minimum feature sizes are reduced for higher integration, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs nested structures where gate electrodes are formed within openings in dielectric layers, and channel layers are positioned within gate electrode structures. This nested approach allows precise feature formation through sequential deposition and patterning steps, reducing the need for extremely tight minimum feature size control.
Solution Approach 2:
Dielectric layers are formed and patterned with openings before gate electrode deposition. This preliminary structuring establishes precise geometric constraints that guide subsequent material deposition, ensuring accurate feature formation without requiring extreme precision in each individual step.
3Device complexity
If off-chip memory access is used, then device complexity is reduced, but energy consumption increases
Solution Approach 1:
The patent integrates memory functions directly within the semiconductor chip by forming three-dimensional memory cells using the same fabrication processes as the main device. This merging of memory and logic on-chip eliminates the need for separate off-chip memory components, reducing energy consumption associated with data transfer while maintaining manageable device complexity through shared process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of three-dimensional memory devices with reduced parasitic capacitance and faster, lower power consumption, suitable for emerging applications like IoT and machine learning, while minimizing footprint and avoiding energy bottlenecks.
Implementation Method 1
lining sidewalls of the openings with a ferroelectric material
Data Source
AI summary
A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.